Stacked semiconductor package and method of manufacturing the same

Claim 2

An integrated circuit package comprising: a substrate having conductive traces therein, the substrate including a cavity therein; a first semiconductor die mounted in a die-down configuration to a first surface of said substrate such that said first semiconductor die spans said cavity; a second semiconductor die mounted to a backside of said first semiconductor die; a first plurality of wire bonds electrically connecting said first semiconductor die to portions of said conductive traces of said substrate; a second plurality of wire bonds connecting said second semiconductor die to other portions of said conductive traces of said substrate; an encapsulant encapsulating said second plurality of wire bonds and covering at least a portion of said first surface of said substrate and said second semiconductor die; a ball grid array disposed on a second surface of said substrate, bumps of said ball grid array being connected with said conductive traces; a second encapsulant, encapsulating said first plurality of wire bonds; and a dummy silicon die disposed on said second semiconductor die.

Claim 3

The integrated circuit package according to claim 1 , wherein the second plurality of wire bonds connect said second semiconductor die to said other portions of said conductive traces, said other portions being disposed on said first side of said substrate.

Claim 4

The integrated circuit package according to claim 1 , wherein the first plurality of wire bonds connect said first semiconductor die to portions of said conductive traces, said portions of said conductive traces being disposed on a second side of said substrate.

Claim 5

The integrated circuit package according to claim 1 , further comprising a heat sink, disposed in said encapsulating material for conducting heat away from said second semiconductor die.

Claim 6

The integrated circuit package according to claim 1 , further comprising a heat sink disposed in said encapsulating material and in contact with said dummy silicon die for conducting heat away from said second semiconductor die.

Claim 7

The integrated circuit package according to claim 5 , wherein said heat sink is disposed on a portion of said second semiconductor die.

Claim 8

An integrated circuit package comprising: a substrate having conductive traces therein; a first semiconductor die mounted in a die-down configuration to a first surface of said substrate; a second semiconductor die mounted to a backside of said first semiconductor die; a plurality of connectors electrically connecting said first semiconductor die to portions of said conductive traces of said substrate; a plurality of wire bonds connecting said second semiconductor die to other portions of said conductive traces of said substrate; an encapsulant encapsulating said wire bonds and covering at least a portion of said first surface of said substrate and said second semiconductor die; and a ball grid array disposed on a second surface of said substrate, bumps of said ball grid array being connected with said conductive traces, wherein said first semiconductor die is a dynamic random access memory chip and said second semiconductor die is a flash memory chip.

Claim 9

An integrated circuit package comprising: a substrate having conductive traces therein; a first semiconductor die mounted in a die-down configuration to a first surface of said substrate; a second semiconductor die mounted to a backside of said first semiconductor die; a plurality of connectors electrically connecting said first semiconductor die to portions of said conductive traces of said substrate; a plurality of wire bonds connecting said second semiconductor die to other portions of said conductive traces of said substrate; an encapsulant encapsulating said wire bonds and covering at least a portion of said first surface of said substrate and said second semiconductor die; and a ball grid array disposed on a second surface of said substrate, bumps of said ball grid array being connected with said conductive traces, wherein said first semiconductor die is a dynamic random access memory chip and said second semiconductor die is a flash memory chip.

Claim 10

A process for fabricating an integrated circuit package, comprising: mounting a first semiconductor die in a die-down configuration, over a cavity in a substrate, the substrate including conductive traces therein; mounting a second semiconductor die to a backside of said first semiconductor die; wire bonding said second semiconductor die to portions of said conductive traces of said substrate; encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate, in an encapsulant; wire bonding said first semiconductor die to other portions of said conductive traces of said substrate; encapsulating the wire bonds between the first semiconductor die and said substrate; and forming a ball and array on a second side of the substrate, bumps of the ball grid array being electrically connected to ones of said conductive traces, wherein said mounting a first semiconductor die comprises mounting a dynamic random access memory chip in a die-down configuration, over said cavity in said substrate.

Claim 11

A process for fabricating an integrated circuit package, comprising: mounting a first semiconductor die in a die-down configuration, over a cavity in a substrate, the substrate including conductive traces therein; mounting a second semiconductor die to a backside of said first semiconductor die; wire bonding said second semiconductor die to portions of said conductive traces of said substrate; encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate, in an encapsulant; wire bonding said first semiconductor die to other portions of said conductive traces of said substrate; encapsulating the wire bonds between the first semiconductor die and said substrate; and forming a ball and array on a second side of the substrate, bumps of the ball grid array being electrically connected to ones of said conductive traces, wherein said mounting a first semiconductor die comprises mounting a dynamic random access memory chip in a die-down configuration, over said cavity in said substrate.

Claim 12

The process for fabricating an integrated circuit package according to claim 8 , wherein said mounting a second semiconductor die comprises mounted a flash memory chip to a backside of said dynamic random access memory chip.

Claim 13

The process for fabricating an integrated circuit package according to claim 9 , wherein said wire bonding said second semiconductor die to portions of said conductive traces of said substrate includes wire bonding the second semiconductor die to said conductive traces on a first side of said substrate.

Claim 14

The process for fabricating an integrated circuit package according to claim 10 , wherein said wire bonding said first semiconductor die to other portions of said conductive traces of said substrate includes wire bonding the first semiconductor die to ones of said conductive traces on the second side of the substrate.

Claim 15

A process for fabricating an integrated circuit package, comprising. mounting a first semiconductor die in a die-down configuration, over a cavity in a substrate, the substrate including conductive traces therein; mounting a second semiconductor die to a backside of said first semiconductor die; wire bonding said second semiconductor die to portions of said conductive traces of said substrate; fixing a dummy silicon die on said second semiconductor die, prior to encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate in an encapsulant; encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate, in the encapsulant; wire bonding said first semiconductor die to other portions of said conductive traces of said substrate; encapsulating the wire bonds between the first semiconductor die and said substrate; and forming a ball arid array on a second side of the substrate, bumps of the ball grid array being electrically connected to ones of said conductive traces.

Claim 16

A process for fabricating an integrated circuit package, comprising. mounting a first semiconductor die in a die-down configuration, over a cavity in a substrate, the substrate including conductive traces therein; mounting a second semiconductor die to a backside of said first semiconductor die; wire bonding said second semiconductor die to portions of said conductive traces of said substrate; fixing a dummy silicon die on said second semiconductor die, prior to encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate in an encapsulant; encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate, in the encapsulant; wire bonding said first semiconductor die to other portions of said conductive traces of said substrate; encapsulating the wire bonds between the first semiconductor die and said substrate; and forming a ball arid array on a second side of the substrate, bumps of the ball grid array being electrically connected to ones of said conductive traces.

Claim 17

A process for fabricating an integrated circuit package, comprising; mounting a first semiconductor die in a die-down configuration, over a cavity in a substrate, the substrate including conductive traces therein; mounting a second semiconductor die to a backside of said first semiconductor die; fixing a dummy silicon die on said second semiconductor die, prior to wire bonding said second semiconductor die to portions of said conductive traces of said substrate, for conducting heat away from said second semiconductor die; wire bonding said second semiconductor die to portions of said conductive traces of said substrate; encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate, in an encapsulant; wire bonding said first semiconductor die to other portions of said conductive traces of said substrate; encapsulating the wire bonds between the first semiconductor die and said substrate; and forming a ball grid array on a second side of the substrate, bumps of the ball grid array being electrically connected to ones of said conductive traces.

Claim 18

A process for fabricating an integrated circuit package, comprising; mounting a first semiconductor die in a die-down configuration, over a cavity in a substrate, the substrate including conductive traces therein; mounting a second semiconductor die to a backside of said first semiconductor die; fixing a dummy silicon die on said second semiconductor die, prior to wire bonding said second semiconductor die to portions of said conductive traces of said substrate, for conducting heat away from said second semiconductor die; wire bonding said second semiconductor die to portions of said conductive traces of said substrate; encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate, in an encapsulant; wire bonding said first semiconductor die to other portions of said conductive traces of said substrate; encapsulating the wire bonds between the first semiconductor die and said substrate; and forming a ball grid array on a second side of the substrate, bumps of the ball grid array being electrically connected to ones of said conductive traces.

Claim 19

The process for fabricating an integrated circuit package according to claim 13 , wherein encapsulating the wire bonds between the second semiconductor die and said conductive traces of said substrate includes molding a heat sink in contact with said dummy silicon die for conducting heat away from said dummy silicon die.