US6809587B2
Expired / Lapsed
US
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Active predistorting linearizer with agile bypass circuit for safe mode operation
Assignee: Mitec Telecom Inc
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Filing: 2002-04-23
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Granted: 2004-10-26
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Expires: 2022-04-23
Abstract
Abstract An active predistorting linearizer with agile bypass circuit for safe mode operation is used in conjunction with an amplifier. This linearizer comprises a controllable input variable-attenuator and drive-amplifier circuit supplied with the input signal to attenuate and amplify the input signal. A predistorter includes a controllable phase-shifting and amplitude-adjusting path supplied with the attenuated and amplified input signal to distort the latter signal and produce a predistorted output signal. A controllable output variable-attenuator and drive-amplifier circuit is supplied with the predistorted output signal to attenuate and amplify this predistorted output signal before supplying it to the power amplifier. A phase-shifting and amplitude-adjusting controller is connected to the controllable input variable-attenuator and drive-amplifier circuit, the controllable phase-shifting and amplitude-adjusting path, and the controllable output variable-attenuator and drive-amplifier circuit. Finally, a bypass extends in parallel with the series circuit including the serially interconnected input variable-attenuator and drive-amplifier circuit, controllable phase-shifting and amplitude-adjusting path, and output variable-attenuator and drive-amplifier circuit. This bypass defines a bypass circuit established in response to a fault condition in the series circuit to bypass the faulty series circuit.
Inventors
- 👤 Fadhel Ghannouchi
- 👤 Said Touimer
- 👤 François Beauregard
- 👤 Chan-Wang Park
- 👤 Ahmed A. Boutouili
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:05
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3241; H03F1/3282; H03F2200/00; H03F2200/198
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
151 words
An open loop predistorter for predistorting a RF signal subsequently injected in an amplifier, comprising: a hybrid coupler comprising a RF input constituting an input of the predistorter supplied with the RF signal, a RF output constituting an output of the predistorter for supplying a predistorted version of the RF signal, a direct port, and a coupled port; a first diode having an anode connected to said direct port and a cathode connected to the ground; a second diode having an anode connected to said coupled port and a cathode connected to the ground; and a controllable biasing-voltage supply connected to said direct port and to said coupled port, thereby supplying said direct and coupled ports with a controllable biasing voltage; wherein, in operation, said open loon predistorter produces a controllable predistortion of the RF signal related to the controllable biasing voltage to cancel a distortion subsequently produced by the amplifier.
Claim 2
Dependent Claim
151 words
An open loop predistorter for predistorting a RF signal subsequently injected in an amplifier, comprising: a hybrid coupler comprising a RF input constituting an input of the predistorter supplied with the RF signal, a RF output constituting an output of the predistorter for supplying a predistorted version of the RF signal, a direct port, and a coupled port; a first diode having an anode connected to said direct port and a cathode connected to the ground; a second diode having an anode connected to said coupled port and a cathode connected to the ground; and a controllable biasing-voltage supply connected to said direct port and to said coupled port, thereby supplying said direct and coupled ports with a controllable biasing voltage; wherein, in operation, said open loon predistorter produces a controllable predistortion of the RF signal related to the controllable biasing voltage to cancel a distortion subsequently produced by the amplifier.
Claim 3
Dependent Claim
39 words
The open loop predistorter as defined in claim 1 , further comprising a first inductor interposed between the controllable biasing-voltage supply and the direct port and a second inductor interposed between said controllable biasing-voltage supply and the coupled port.
Claim 4
Dependent Claim
43 words
The open loop predistorter as in claim 1 further comprising a first matching circuit interposed between the direct port and the anode of the first diode and a second matching circuit interposed between the coupled port and the anode of the second diode.
Claim 5
Dependent Claim
21 words
The open loop predistorter as defined in claim 3 , wherein the first and second matching circuits are matching line circuits.
Claim 6
Dependent Claim
19 words
The open loop predistorter as defined in claim 1 , wherein said first and second diodes are Schottky diodes.
Claim 7
Dependent Claim
32 words
The open loop predistorter as defined in claim 1 , wherein said controllable predistortion of the RF signal can be bypassed by setting said controllable biasing voltage to below an operational threshold.
Claim 8
Dependent Claim
179 words
A predistorting linearizer channel amplifier for processing an input signal subsequently supplied to a power amplifier, comprising: a controllable input variable-attenuator and drive-amplifier circuit supplied with the input signal to attenuate and amplify said input signal; a predistorter comprising a controllable phase-shifting and amplitude-adjusting path supplied with the attenuated and amplified input signal to distort said attenuated and amplified input signal and produce a predistorted output signal; a controllable output variable-attenuator and drive-amplifier circuit supplied with the predistorted output signal to attenuate and amplify the predistorted output signal before supplying said predistorted output signal to the power amplifier; a phase-shifting and amplitude-adjusting controller connected to the controllable input variable-attenuator and drive-amplifier circuit, the controllable phase-shifting and amplitude-adjusting path, and the controllable output variable-attenuator and drive-amplifier circuit; and a bypass extending in parallel with the series circuit including the serially interconnected input variable-attenuator and drive-amplifier circuit, controllable phase-shifting and amplitude-adjusting path, and output variable-attenuator and drive-amplifier circuit, said bypass defining a bypass circuit established in response to a fault condition in said series circuit to bypass the faulty series circuit.
Claim 9
Dependent Claim
179 words
A predistorting linearizer channel amplifier for processing an input signal subsequently supplied to a power amplifier, comprising: a controllable input variable-attenuator and drive-amplifier circuit supplied with the input signal to attenuate and amplify said input signal; a predistorter comprising a controllable phase-shifting and amplitude-adjusting path supplied with the attenuated and amplified input signal to distort said attenuated and amplified input signal and produce a predistorted output signal; a controllable output variable-attenuator and drive-amplifier circuit supplied with the predistorted output signal to attenuate and amplify the predistorted output signal before supplying said predistorted output signal to the power amplifier; a phase-shifting and amplitude-adjusting controller connected to the controllable input variable-attenuator and drive-amplifier circuit, the controllable phase-shifting and amplitude-adjusting path, and the controllable output variable-attenuator and drive-amplifier circuit; and a bypass extending in parallel with the series circuit including the serially interconnected input variable-attenuator and drive-amplifier circuit, controllable phase-shifting and amplitude-adjusting path, and output variable-attenuator and drive-amplifier circuit, said bypass defining a bypass circuit established in response to a fault condition in said series circuit to bypass the faulty series circuit.
Claim 10
Dependent Claim
55 words
A predistorting linearizer channel amplifier as defined in claim 7 , wherein: the controllable input variable-attenuator and drive-amplifier circuit comprises a first controllable variable attenuator and an input drive amplifier connected in series; and the controllable output variable-attenuator and drive-amplifier circuit comprises a second controllable variable attenuator and an output drive amplifier connected in series.
Claim 11
Dependent Claim
207 words
A predistorting linearizer channel amplifier as recited in claim 7 , further comprising: a main input supplied with the input signal; a main output to deliver the attenuated and amplified predistorted output signal to the power amplifier; said bypass comprising: a signal amplifier having an input and an output; a controllable input switch interposed between the main Input, an input of the input variable-attenuator and drive-amplifier circuit, and the input of the signal amplifier, said input switch having a first position defining a conductive path between the main input and the input of the input variable-attenuator and drive-amplifier circuit and a second position defining a conductive path between the main input and the input of the signal amplifier; a controllable output switch interposed between an output of the output variable-attenuator and drive-amplifier circuit, the output of the signal amplifier, and the main output, said output switch having a first position defining a conductive path between the output of the output variable-attenuator and drive-amplifier circuit and the main output, and a second position defining a conductive path between the output of the signal amplifier and the main output; and an input and output switch control responsive to said fault and connected to both said input and output switches.
Claim 12
Dependent Claim
78 words
A predistorting linearizer channel amplifier as defined in claim 9 , wherein the input and output switch control comprises a detector of said input signal, an attenuated and amplified predistorted output signal detector, a comparator of the input and output signals detected by said signal detectors, a fault condition detector responsive to the comparison between the detected input and output signals, and a switching control unit interposed between the fault condition detector and the input and output switches.
References Cited (Backward Citations)
US4412337A
Cited
US6255908B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-10-26 | 2008-04-26 | 2008-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-10-26 | 2012-04-26 | 2012-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-10-26 | 2016-04-26 | 2016-10-26 | $7700.00 | Window Closed / Lapsed |