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US6808971B2 Expired / Lapsed US ⏱️ 0.0 years remaining

High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters

Assignee: Round Rock Research LLC
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Filing: 2004-01-14
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Granted: 2004-10-26
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Expires: 2024-01-14
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Abstract

Abstract The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a semiconductor-on-insulator thin film transistor construction, and can be formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The thin film of semiconductor material can comprise both silicon and germanium. Further, the thin film can contain two different layers. A first of the two layers can have silicon and germanium present in a relaxed crystalline lattice, and a second of the two layers can be a strained crystalline lattice of either silicon alone, or silicon in combination with germanium. The invention also includes computer systems utilizing such CMOS inverters.

Inventors

  • 👤 Arup Bhattacharyya

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 08:23
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/201; H10D88/00; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6748

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 111 words
A method of forming a CMOS inverter, comprising: providing a substrate; forming a PFET device supported by the substrate, the PFET device comprising a gate and a p-type doped source/drain region proximate the gate; epitaxially growing a semiconductive material pillar over the p-type source/drain region; doping the pillar with p-type dopant; epitaxially growing a silicon-containing seed layer over the pillar; forming crystalline Si/Ge over the silicon-containing seed layer; and forming an NFET device supported by the crystalline Si/Ge, the NFET device comprising a gate and an n-type doped source/drain region proximate the gate; and the pillar being an electrical connection from the p-type doped source/drain region to the n-type source/drain region.
Claim 2
Independent Claim 111 words
A method of forming a CMOS inverter, comprising: providing a substrate; forming a PFET device supported by the substrate, the PFET device comprising a gate and a p-type doped source/drain region proximate the gate; epitaxially growing a semiconductive material pillar over the p-type source/drain region; doping the pillar with p-type dopant; epitaxially growing a silicon-containing seed layer over the pillar; forming crystalline Si/Ge over the silicon-containing seed layer; and forming an NFET device supported by the crystalline Si/Ge, the NFET device comprising a gate and an n-type doped source/drain region proximate the gate; and the pillar being an electrical connection from the p-type doped source/drain region to the n-type source/drain region.
Claim 3
Dependent Claim 21 words
The method of claim 1 wherein the doping of the pillar comprises out-diffusion of dopant from the p-type doped source/drain region.
Claim 4
Dependent Claim 15 words
The method of claim 1 wherein the forming the crystalline Si/Ge comprises metal-induced lateral recrystallization.
Claim 5
Dependent Claim 57 words
The method of claim 1 wherein the crystalline Si/Ge comprises a relaxing crystalline lattice, and further comprising forming a semiconductive material having a strained crystalline lattice over the Si/Ge; the NFET device gate being formed over the material having the strained crystalline lattice and having a channel region extending into the material having the strained crystalline lattice.
Claim 6
Dependent Claim 15 words
The method of claim 4 wherein the material having the strained crystalline lattice includes silicon.
Claim 7
Dependent Claim 17 words
The method of claim 4 wherein the material having the strained crystalline lattice includes silicon and germanium.
Claim 8
Dependent Claim 16 words
The method of claim 4 further comprising doping the epitaxially grown seed layer with p-type dopant.

References Cited (Backward Citations)

US4768076A Cited
US4692994A Cited
US5006913A Cited
US6429085B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2007-10-26 2008-04-26 2008-10-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2011-10-26 2012-04-26 2012-10-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2015-10-26 2016-04-26 2016-10-26 $7700.00 Window Closed / Lapsed

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