US6806534B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Damascene method for improved MOS transistor
Assignee: GlobalFoundries Inc
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Filing: 2003-01-14
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Granted: 2004-10-19
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Expires: 2023-01-14
Abstract
Abstract A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
Inventors
- 👤 Omer H. Dokumaci
- 👤 Bruce B. Doris
- 👤 Oleg Gluschenkov
- 👤 Jack A. Mandelman
- 👤 Carl J. Radens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:38
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D30/0212; H10D64/018; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
207 words
Method for fabricating a high performance MOSFET device having a novel gate structure comprising the steps of: a) providing a structure of at least one pad layers to function as a mandrel over a semiconductor substrate, said one or more pad layers having an aperture; b) depositing a high density plasma dielectric material within said aperture; c) forming respective spacer elements on either sidewall of said aperture overlying said high density plasma dielectric material in said aperture; d) removing a portion of said high density plasma dielectric material not underlying said spacer elements within said aperture, forming high density plasma dielectric placeholders defining a region of sub-lithographic width; e) forming a gate dielectric in said region, wherein said gate dielectric is positioned between said high density plasma dielectric placeholders; f) forming a first gate conductor material in said region to form a sub-lithographic lower gate conducting portion within said aperture; g) depositing a second gate conductor material to form an upper gate conducting portion within said aperture having a dimension that is wider than said sub-lithographic lower gate conducting portion, and self-aligned to said sub-lithographic lower gate conductor portion; wherein a resulting MOSFET device includes a sub-lithographic channel length according to said sub-lithographic lower gate conducting portion.
Claim 2
Dependent Claim
207 words
Method for fabricating a high performance MOSFET device having a novel gate structure comprising the steps of: a) providing a structure of at least one pad layers to function as a mandrel over a semiconductor substrate, said one or more pad layers having an aperture; b) depositing a high density plasma dielectric material within said aperture; c) forming respective spacer elements on either sidewall of said aperture overlying said high density plasma dielectric material in said aperture; d) removing a portion of said high density plasma dielectric material not underlying said spacer elements within said aperture, forming high density plasma dielectric placeholders defining a region of sub-lithographic width; e) forming a gate dielectric in said region, wherein said gate dielectric is positioned between said high density plasma dielectric placeholders; f) forming a first gate conductor material in said region to form a sub-lithographic lower gate conducting portion within said aperture; g) depositing a second gate conductor material to form an upper gate conducting portion within said aperture having a dimension that is wider than said sub-lithographic lower gate conducting portion, and self-aligned to said sub-lithographic lower gate conductor portion; wherein a resulting MOSFET device includes a sub-lithographic channel length according to said sub-lithographic lower gate conducting portion.
Claim 3
Dependent Claim
27 words
The method according to claim 1 , further comprising the step of doping said lower gate conducting portion for minimizing gate depletion effects during MOSFET device operation.
Claim 4
Dependent Claim
50 words
The method according to claim 2 , further performing, after the step of forming said second gate conductor material atop said lower gate conducting portion, the steps of recessing a top portion of said upper gate conducting portion and depositing a dielectric cap layer atop said upper gate conducting portion.
Claim 5
Dependent Claim
39 words
The method according to claim 1 , further comprising forming an insulating second spacer along each sidewall of said high density plasma dielectric placeholders, prior to depositing said gate dielectric, wherein said insulating second spacer protects said gate dielectric.
Claim 6
Dependent Claim
34 words
The method according to claim 1 , wherein said at least one pad layers include an oxide pad layer formed atop said substrate and a nitride pad layer formed atop said oxide pad layer.
Claim 7
Dependent Claim
41 words
The method according to claim 1 , wherein said step f) comprises depositing said first gate conductor material in said aperture and recessing said first gate conductor material in said aperture to a level below said high density plasma dielectric placeholders.
Claim 8
Dependent Claim
41 words
The method according to claim 1 , wherein said step g) comprises the steps of depositing said second gate conductor material atop said lower gate conducting portion to the surface of said at least one pad layers and planarizing the surface.
Claim 9
Dependent Claim
18 words
The method according to claim 1 , wherein said first gate conductor material comprises polysilicon, SiGe or SiGeC.
Claim 10
Dependent Claim
31 words
The method according to claim 1 , wherein said second gate conductor material comprises polysilicon, SiGe, SiGeC, metals, metal nitrides, metal silicides, refractory metals, refractory metals or silicides or nitrides thereof.
Claim 11
Dependent Claim
69 words
The method according to claim 1 , further including the steps of: h) removing said at least one pad layers to expose said upper and lower gate conducting portions of said gate structure; i) providing source and drain implants in said substrate at respective source and drain regions adjacent said gate structure; and j) forming sidewall spacers surrounding said gate structure and extending to said source and drain regions.
Claim 12
Dependent Claim
25 words
The method according to claim 10 , further including the step of doping said source and drain regions to facilitate later formation of a contact.
Claim 13
Dependent Claim
23 words
The method according to claim 1 , wherein said upper gate conducting portion is of a width longer than a minimum lithographic image.
Claim 14
Dependent Claim
82 words
A high performance MOSFET device comprising: a substrate; a gate dielectric layer of defined sub-lithographic width, defining a sub-lithographic channel; a lower gate conducting portion formed on said gate dielectric layer, where said lower gate conducting portion includes a set of notches to reduce the width of said lower gate conducting portion; an upper gate conducting portion self-aligned to and wider than said lower gate conducting portion; and a source and drain diffusion region formed on either side of said sub-lithographic channel.
Claim 15
Dependent Claim
82 words
A high performance MOSFET device comprising: a substrate; a gate dielectric layer of defined sub-lithographic width, defining a sub-lithographic channel; a lower gate conducting portion formed on said gate dielectric layer, where said lower gate conducting portion includes a set of notches to reduce the width of said lower gate conducting portion; an upper gate conducting portion self-aligned to and wider than said lower gate conducting portion; and a source and drain diffusion region formed on either side of said sub-lithographic channel.
Claim 16
Dependent Claim
29 words
The high performance MOSFET device of claim 13 , wherein said lower gate conducting portion is doped to minimize effects of electrical depletion of carriers during MOSFET device operations.
Claim 17
Dependent Claim
27 words
The high performance MOSFET device of claim 13 , wherein said upper gate conducting portion comprising polysilicon, SiGe, SiGeC, metal, silicide, metallic nitride, or other conductive materials.
Claim 18
Dependent Claim
20 words
The high performance MOSFET device of claim 13 , wherein said upper gate conducting portion is capped with an insulator.
Claim 19
Dependent Claim
26 words
The high performance MOSFET device of claim 13 , wherein said lower gate conducting portion has a width that is less than a lithographic minimum image.
Claim 20
Dependent Claim
33 words
The high performance MOSFET device of claim 13 , wherein said lower gate conducting portion is flanked by a set of spacers which protect said lower gate conducting portion during etch process steps.
References Cited (Backward Citations)
US5182225A
Cited
US6054355A
Cited
JPH11233646A
Cited
US6040214A
Cited
US6143635A
Cited
US20020192911A1
Cited
US20020197810A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-10-19 | 2008-04-19 | 2008-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-10-19 | 2012-04-19 | 2012-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-10-19 | 2016-04-19 | 2016-10-19 | $7700.00 | Window Closed / Lapsed |