US6788594B2
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US
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Asynchronous, high-bandwidth memory component using calibrated timing elements
Assignee: Rambus Inc
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Filing: 2002-10-15
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Granted: 2004-09-07
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Expires: 2022-10-15
Abstract
Abstract Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
Inventors
- 👤 Frederick A. Ware
- 👤 Ely K. Tsern
- 👤 Craig E. Hampel
- 👤 Donald C. Stark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:56
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C29/00; G11C29/02; G11C29/028; G11C29/04; G11C29/50; G11C29/50012; G11C7/1015; G11C7/1039; G11C7/106; G11C7/1078; G11C7/1087; G11C7/22; G11C2207/00; G11C2207/22; G11C2207/2254; G11C7/04
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
112 words
A memory device comprising: memory access logic that receives memory access initiation signals and performs pipelined memory access cycles in response, the memory access logic having pipeline elements that are signaled in sequence to complete the memory access cycles; matched delay elements that are collectively adjustable to produce matching delays that are asynchronous within the memory device; the matched delay elements being configured to produce asynchronously timed pipeline load signals in response to the memory access initiation signals, to load the pipeline elements of the memory access logic in sequence, wherein the matched delay elements are calibrated to one or more calibration signals received from a source external to the memory device.
Claim 2
Dependent Claim
112 words
A memory device comprising: memory access logic that receives memory access initiation signals and performs pipelined memory access cycles in response, the memory access logic having pipeline elements that are signaled in sequence to complete the memory access cycles; matched delay elements that are collectively adjustable to produce matching delays that are asynchronous within the memory device; the matched delay elements being configured to produce asynchronously timed pipeline load signals in response to the memory access initiation signals, to load the pipeline elements of the memory access logic in sequence, wherein the matched delay elements are calibrated to one or more calibration signals received from a source external to the memory device.
Claim 3
Dependent Claim
59 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the received calibration signal.
Claim 4
Dependent Claim
73 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the received calibration signal; and wherein the delay calibration logic operates periodically to adjust the matched delay elements.
Claim 5
Dependent Claim
69 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the received calibration signal; and wherein the calibration signal comprises two relatively timed events.
Claim 6
Dependent Claim
82 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the received calibration signal; and wherein the calibration signal is received on a single input conductor from the external source and comprises two relatively timed signal transitions.
Claim 7
Dependent Claim
81 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the received calibration signal; and wherein the calibration signal is received on two input conductors from the external source and comprises two relatively timed signal transitions.
Claim 8
Dependent Claim
70 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the received calibration signal; and wherein the calibration signal is asynchronous within the memory device.
Claim 9
Dependent Claim
89 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the received calibration signal; and wherein the memory access logic receives memory access initiation signals on a particular input conductor; and wherein the calibration logic receives the calibration signal on said particular input conductor.
Claim 10
Dependent Claim
92 words
A memory device as recited in claim 1 , further comprising: delay calibration logic that includes at least one of the matched delay elements, wherein the delay calibration logic receives a calibration signal and collectively adjusts the matched delay elements until said at least one of the matched, delay elements has a delay corresponding to the received calibration signal; and wherein the memory access initiation signals comprise address load signals that are received on a particular input conductor; and wherein the calibration logic receives the calibration signal on said particular input conductor.
Claim 11
Dependent Claim
77 words
A memory device comprising; one or more address registers that load a received memory address at a time indicated by a received input load signal; one or more delay elements that asynchronously delay the received input load signal; a memory access logic that is responsive to the delayed input load signal to perform a memory operation; wherein the delay elements are calibrated to one or more calibration signals received from a source external to the memory device.
Claim 12
Dependent Claim
77 words
A memory device comprising; one or more address registers that load a received memory address at a time indicated by a received input load signal; one or more delay elements that asynchronously delay the received input load signal; a memory access logic that is responsive to the delayed input load signal to perform a memory operation; wherein the delay elements are calibrated to one or more calibration signals received from a source external to the memory device.
Claim 13
Dependent Claim
38 words
A memory device as recited in claim 10 , wherein the one or more delay elements comprise a plurality of matched delay elements that are collectively adjustable to produce matching delays that are asynchronous within the memory device.
Claim 14
Dependent Claim
87 words
A memory device as recited in claim 10 , wherein: the one or more delay elements comprise a plurality of matched delay elements that are collectively adjustable to produce matching delays that are asynchronous within the memory device; the memory device further comprises delay calibration logic that includes at least one of the matched delay elements; the delay calibration logic collectively adjusts the matched delay elements until said at least one of the matched delay elements has a delay corresponding to the one or more calibration signals.
Claim 15
Dependent Claim
23 words
A memory device as recited in claim 10 , wherein the delay elements are calibrated periodically to the one or more calibration signals.
Claim 16
Dependent Claim
20 words
A memory device as recited in claim 10 , wherein the one or mote delay elements are calibrated using feedback.
Claim 17
Dependent Claim
22 words
A memory device as recited in claim 10 , wherein the one or more calibration signals comprise two relatively timed signal transitions.
Claim 18
Dependent Claim
18 words
A memory device as recited in claim 10 , wherein the memory operation is a cell read operation.
Claim 19
Dependent Claim
18 words
A memory device as recited in claim 10 , wherein the memory operation is a cell write operation.
Claim 20
Dependent Claim
18 words
A memory device as recited in claim 10 , wherein the memory operation is a cell sense operation.
Claim 21
Dependent Claim
18 words
A memory device as recited in claim 10 , wherein the memory operation is a cell precharge operation.
Claim 22
Dependent Claim
31 words
A memory device as recited in claim 10 , wherein the one or more delay elements are configurable, after device manufacture, to delay the received input load signal by different times.
Claim 23
Dependent Claim
28 words
A memory device as recited in claim 10 , wherein the one or more calibration signals are received on a conductor that also carries the input load signal.
Claim 24
Dependent Claim
22 words
A memory device as recited in claim 10 , wherein the one or more calibration signals are encoded on an address bus.
Claim 25
Dependent Claim
22 words
A memory device as recited in claim 10 , wherein the one or more calibration signals are encoded on a command bus.
Claim 26
Dependent Claim
22 words
A memory device as recited in claim 10 , wherein the one or more calibration signals are encoded on a data bus.
Claim 27
Independent Claim
71 words
A method of accessing a memory device comprising: performing pipelined memory access cycles in response to receiving memory access initiation signals; generating asynchronously-timed pipeline load signals to load pipeline elements within the memory device in sequence, the pipeline load signals being generated by matched delay elements; and calibrating one or more of the matched delay elements to one or more calibration signals received from a source external to the memory device.
Claim 28
Independent Claim
71 words
A method of accessing a memory device comprising: performing pipelined memory access cycles in response to receiving memory access initiation signals; generating asynchronously-timed pipeline load signals to load pipeline elements within the memory device in sequence, the pipeline load signals being generated by matched delay elements; and calibrating one or more of the matched delay elements to one or more calibration signals received from a source external to the memory device.
Claim 29
Dependent Claim
32 words
A method of accessing a memory device as recited in claim 25 , wherein the matched delay elements are collectively adjustable to generate matching delays that are asynchronous within the memory device.
Claim 30
Dependent Claim
41 words
A method of accessing a memory device as recited in claim 25 , further comprising collectively adjusting the matched delay elements until at least one of the matched delay elements has a delay corresponding to the one or more calibration signals.
Claim 31
Dependent Claim
30 words
A method of accessing a memory device as recited in claim 25 , wherein the generating asynchronously-timed pipeline load signals is performed in response to the memory access initiation signals.
Claim 32
Dependent Claim
27 words
A method of accessing a memory device as recited in claim 25 , further comprising signaling the pipeline elements in sequence to complete the memory access cycles.
Claim 33
Dependent Claim
19 words
A method of accessing a memory device as recited in claim 25 , wherein the calibrating is performed periodically.
Claim 34
Independent Claim
73 words
A method comprising: loading one or more address registers of a memory device with a received memory address at a time indicated by a received input load signal; asynchronously delaying the received input load signal through one or more delay elements; accessing the memory device in response to the delayed input load signal; and calibrating the delay elements to one or more calibration signals received from a source external to the memory device.
Claim 35
Independent Claim
73 words
A method comprising: loading one or more address registers of a memory device with a received memory address at a time indicated by a received input load signal; asynchronously delaying the received input load signal through one or more delay elements; accessing the memory device in response to the delayed input load signal; and calibrating the delay elements to one or more calibration signals received from a source external to the memory device.
Claim 36
Dependent Claim
37 words
A method as recited in claim 31 , wherein the one or more delay elements comprise a plurality of matched delay elements that are collectively adjustable to produce matching delays that are asynchronous within the memory device.
Claim 37
Dependent Claim
87 words
A method as recited in claim 31 , wherein: the one or more delay elements comprise a plurality of matched delay elements that are collectively adjustable to produce matching delays that are asynchronous within the memory device; the memory device further comprises delay calibration lope that includes at least one of the matched delay elements; and the delay calibration logic collectively adjusts the matched delay elements until the at least one of the matched delay elements has a delay corresponding to the one or more calibration signals.
Claim 38
Dependent Claim
22 words
A method as recited in claim 31 , wherein the delay elements are calibrated periodically to the one or more calibration signals.
Claim 39
Dependent Claim
19 words
A method as recited in claim 31 , wherein the one or more delay elements are calibrated using feedback.
Claim 40
Dependent Claim
21 words
A method as recited in claim 31 , wherein the one or more calibration signals comprise two relatively timed signal transitions.
Claim 41
Dependent Claim
17 words
A method as recited in claim 31 , wherein the memory operation is a cell read operation.
Claim 42
Dependent Claim
17 words
A method as recited in claim 31 , wherein the memory operation is a cell write operation.
Claim 43
Dependent Claim
17 words
A method as recited in claim 31 , wherein the memory operation is a cell sense operation.
Claim 44
Dependent Claim
17 words
A method as recited in claim 31 , wherein the memory operation is a cell precharge operation.
Claim 45
Dependent Claim
31 words
A method as recited in claim 31 , wherein, after the device manufacture, the one or more delay elements are configurable to delay the received input load signal by different times.
Claim 46
Dependent Claim
27 words
A method as recited in claim 31 , wherein the one or more calibration signals are received on a conductor that also carries the input load signal.
Claim 47
Dependent Claim
21 words
A method as recited in claim 31 , wherein the one or more calibration signals are encoded on an address bus.
Claim 48
Dependent Claim
21 words
A method as recited in claim 31 , wherein the one or more calibration signals are encoded on a command bus.
Claim 49
Dependent Claim
21 words
A method as recited in claim 31 , wherein the one or more calibration signals are encoded on a data bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-09-07 | 2008-03-08 | 2008-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-09-07 | 2012-03-08 | 2012-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-09-07 | 2016-03-08 | 2016-09-07 | $7700.00 | Window Closed / Lapsed |