US6785874B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Layout verification method, program thereof, and layout verification apparatus
Assignee: NEC Electronics Corp
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Filing: 2002-07-11
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Granted: 2004-08-31
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Expires: 2022-07-11
Abstract
Abstract Provided are a layout verification apparatus and a layout verification method, each employing an L/S matrix to achieve higher accuracy of verification, as well as a program thereof. The layout verification method is realized by dividing each segment in accordance with the layout of its surrounding other polygon. For instance, in FIG. 3 , since the left side of polygon (P 1 ) (i.e., segment Segc) is, over its entire segment length, most adjacent to polygon (P 5 ), this side is not divided. Since the upper side of the polygon (P 1 ) is, only in part of its segment length, most adjacent to polygon (P 7 ) within distance (R), this side is divided into segment (Segb 1 ) that corresponds to the part adjacent to the polygon (P 7 ), and segment (Segb 2 ) that is the rest. Then, the L/S matrix is referred to segment by segment, to judge whether the polygon can be resolved.
Inventors
- 👤 Eiji Tsukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:20
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
187 words
A layout verification method using a layout data of a semiconductor integrated circuit, said layout data containing plural polygons indicating wiring patterns, said polygons being made up of plural segments that are sides, said method comprising the steps of: (a) dividing plural segments forming one of said plural polygons in said layout data, based on a predetermined rule defined beforehand relative to the layout of other surrounding polygon; (b) with respect to said segments divided and segments not divided, detecting a width of wiring containing each of said segments and a width of space most adjacent to each of said segments; (c) evaluating the possibility of resolution of each of said segments by referring to data of conditions under which resolution can be performed, in which a predetermined conditione relative to the possibility of resolution of said segments in a wafer process is stored in association with a combination of said width of wiring and said width of space; and (d) outputting an error information when there is a segment of which possibility of resolution is negative based on the result of evaluation in said step (c).
Claim 2
Dependent Claim
187 words
A layout verification method using a layout data of a semiconductor integrated circuit, said layout data containing plural polygons indicating wiring patterns, said polygons being made up of plural segments that are sides, said method comprising the steps of: (a) dividing plural segments forming one of said plural polygons in said layout data, based on a predetermined rule defined beforehand relative to the layout of other surrounding polygon; (b) with respect to said segments divided and segments not divided, detecting a width of wiring containing each of said segments and a width of space most adjacent to each of said segments; (c) evaluating the possibility of resolution of each of said segments by referring to data of conditions under which resolution can be performed, in which a predetermined conditione relative to the possibility of resolution of said segments in a wafer process is stored in association with a combination of said width of wiring and said width of space; and (d) outputting an error information when there is a segment of which possibility of resolution is negative based on the result of evaluation in said step (c).
Claim 3
Dependent Claim
57 words
The layout verification method according to claim 1 , wherein; said predetermined rule means that: no division is performed when one segment is, over its entire length, most adjacent to said other polygon; and division is performed when one segment is, only in part of its length, most adjacent to said other polygon within a predetermined distance.
Claim 4
Dependent Claim
80 words
The layout verification method according to claim 1 , wherein; a layout correction amount of each of said segments is stored in said data of conditions under which resolution can be performed, said method further comprising the step of: (e) when said error information is outputted in said step (d), correcting by said correction amount the layout of a segment of which possibility of resolution is negative, while referring to said data of conditions under which resolution can be performed.
Claim 5
Dependent Claim
87 words
The layout verification method according to claim 1 , wherein; in said combination of said width of wiring and said width of space in said data of conditions under which resolution can be performed, there is included a combination of a width of wiring containing an aimed segment of said segments and a width of space most adjacent to said aimed segment, as well as a width of wiring not containing said aimed segment and/or a width of space not being most adjacent to said aimed segment.
Claim 6
Dependent Claim
39 words
The layout verification method according to claim 1 , wherein; said polygons contained in said layout data are wiring patterns of oblique lines where said wiring and said space are disposed obliquely at a predetermined angle on a plane.
Claim 7
Dependent Claim
41 words
The layout verification method according to claim 1 , wherein; said polygons contained in said layout data are hole patterns taking said width of wiring as a hole diameter and said width of space as a width of space between holes.
Claim 8
Dependent Claim
20 words
The layout verification method according to claim 1 , wherein; said predetermined condition is defined based on a defocus margin.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-08-31 | 2008-03-01 | 2008-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-08-31 | 2012-03-01 | 2012-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-08-31 | 2016-03-01 | 2016-08-31 | $7700.00 | Window Closed / Lapsed |