Digital signal modulation system

Claim 2

In a system for processing a digital input signal, a method for producing a coded output signal as a function of a change in a single variable parameter including a logic state of said input signal, comprising the steps of: generating a first pulse width coded bit with a predetermined duration of a multiple of a basic clock period when said input signal represents no change of said parameter; generating a second pulse width coded bit when said input signal represents a first type of change in said parameter; and generating a third pulse width coded bit when said input signal represents a second type of change in said parameter, wherein said first to third pulse width coded bits are different in duration from one another by integral multiples of said basic clock period.

Claim 3

A method according to claim 1 , wherein said parameter is a change in the logic state of said input signal; said first type of change is a logic state change in one direction; and said second type of change is a logic state change in a second direction.

Claim 4

A method according to claim 1 , wherein: said step of generating said first coded bit produces a coded bit with a predetermined reference bit width; said step of generating said second coded bit produces a coded bit with a first predetermined change in bit width relative to said reference bit width; and said step of generating said third coded bit produces a coded bit with a second predetermined change in bit width relative to said reference bit width.

Claim 5

A method according to claim 1 , further comprising the step of processing said coded output signal by a spread spectrum system.

Claim 6

A method according to claim 4 , wherein said processing step includes the steps of modulating said coded output signal on a carrier to produce a modulated signal; and mixing said modulated signal with a pseudorandom noise signal to produce a spread spectrum signal; and transmitting said spread spectrum signal.

Claim 7

A method according to claim 5 , further including the step of low pass filtering said modulated signal prior to said mixing step.

Claim 8

In a system for processing a digital input signal a method for producing a coded output signal as a function of a change in a parameter including a logic state of said input signal, comprising the steps of: generating a first pulse width coded bit with a predetermined duration and a predetermined reference bit width when said input signal represents no change of said parameter; generating a second pulse width coded bit when said input signal represents a first type of change in said parameter, said step of generating said second coded bit produces a coded bit with a first predetermined change in bit width comprising a predetermined increase in bit width relative to said reference bit width, when said input signal exhibits a logic state change in one direction; and generating a third pulse width coded bit when said input signal represents a second type of change in said parameter, wherein said first to third pulse width coded bits are different from one another; and said step of generating said third coded bit produces a third coded bit with a second predetermined change in bit width comprising a predetermined decrease in bit width relative to said reference bit width, when said input signal exhibits a logic state change in another direction.

Claim 9

In a system for processing a digital input signal a method for producing a coded output signal as a function of a change in a parameter including a logic state of said input signal, comprising the steps of: generating a first pulse width coded bit with a predetermined duration and a predetermined reference bit width when said input signal represents no change of said parameter; generating a second pulse width coded bit when said input signal represents a first type of change in said parameter, said step of generating said second coded bit produces a coded bit with a first predetermined change in bit width comprising a predetermined increase in bit width relative to said reference bit width, when said input signal exhibits a logic state change in one direction; and generating a third pulse width coded bit when said input signal represents a second type of change in said parameter, wherein said first to third pulse width coded bits are different from one another; and said step of generating said third coded bit produces a third coded bit with a second predetermined change in bit width comprising a predetermined decrease in bit width relative to said reference bit width, when said input signal exhibits a logic state change in another direction.

Claim 10

In a system for processing a digital input signal, a method for producing a coded output signal as a function of a change in a parameter including a logic state of said input signal, comprising the steps of: generating a first pulse width coded bit with a predetermined duration and a predetermined reference bit width when said input signal represents no change of said parameter; said step of generating said first coded bit produces a coded bit encompassing a predetermined number of clock periods when said input signal does not exhibit a logic state change; generating a second pulse width coded bit when said input signal represents a first type of change in said parameter, said step of generating said second coded bit produces a coded bit encompassing a first predetermined change in bit width comprising a predetermined increase in clock periods when said input signal exhibits a logic state change in one direction; and generating a third pulse width coded bit when said input signal represents a second type of change in said parameter, wherein said first to third pulse width coded bits are different from one another; and said step of generating said third coded bit produces a coded bit with a second predetermined change in bit width relative to said reference bit width encompassing a predetermined decrease in clock periods when said input signal exhibits a logic state change in another direction.

Claim 11

In a system for processing a digital input signal, a method for producing a coded output signal as a function of a change in a parameter including a logic state of said input signal, comprising the steps of: generating a first pulse width coded bit with a predetermined duration and a predetermined reference bit width when said input signal represents no change of said parameter; said step of generating said first coded bit produces a coded bit encompassing a predetermined number of clock periods when said input signal does not exhibit a logic state change; generating a second pulse width coded bit when said input signal represents a first type of change in said parameter, said step of generating said second coded bit produces a coded bit encompassing a first predetermined change in bit width comprising a predetermined increase in clock periods when said input signal exhibits a logic state change in one direction; and generating a third pulse width coded bit when said input signal represents a second type of change in said parameter, wherein said first to third pulse width coded bits are different from one another; and said step of generating said third coded bit produces a coded bit with a second predetermined change in bit width relative to said reference bit width encompassing a predetermined decrease in clock periods when said input signal exhibits a logic state change in another direction.

Claim 12

A method according to claim 8 , wherein said first coded bit encompasses N predetermined clock periods; said second coded bit encompasses N+1 clock periods; and said third coded bit encompasses N−1 clock periods; wherein N is greater than 1.

Claim 13

A method according to claim 9 , wherein N is less than 15.

Claim 14

A decoding method for producing a decoded datastream from a received bitstream comprising first, second and third pulse width coded bits representing changes in a single variable parameter of an input datastream, said decoding method comprising the steps of generating a first data component representing no change of said parameter, in response to said first coded bit of predetermined duration equal to a multiple of a basic clock period; generating a second data component representing a first type of change in said parameter, in response to said second coded bit; and generating a third data component representing a second type of change in said parameter, in response to said third coded bit, wherein said first to third pulse width coded bits are different in duration from one another by integral multiples of said basic clock period.

Claim 15

A decoding method for producing a decoded datastream from a received bitstream comprising first, second and third pulse width coded bits representing changes in a single variable parameter of an input datastream, said decoding method comprising the steps of generating a first data component representing no change of said parameter, in response to said first coded bit of predetermined duration equal to a multiple of a basic clock period; generating a second data component representing a first type of change in said parameter, in response to said second coded bit; and generating a third data component representing a second type of change in said parameter, in response to said third coded bit, wherein said first to third pulse width coded bits are different in duration from one another by integral multiples of said basic clock period.

Claim 16

A decoding method according to claim 11 , wherein said parameter is a logic state of said input datastream; said first data component represents no change in said logic state; said second data component represents a change in said logic state in one direction; and said third data component represents a change in said logic state in another direction.

Claim 17

A decoding method for producing a decoded datastream from a received bitstream comprising first, second and third pulse width coded bits representing chances in a single variable parameter of an input datastream said decoding method comprising the steps of generating a first data component representing no change of said parameter, in response to said first coded bit of predetermined duration equal to a multiple of a basic clock period; generating a second data component representing a first type of chance in said parameter, in response to said second coded bit; and generating a third data component representing a second type of change in said parameter, in response to said third coded bit, wherein said first to third pulse width coded bits are different in duration from one another; wherein said first coded bit encompasses N predetermined clock periods; said second coded bit encompasses N+1 clock periods; and said third coded bit encompasses N−1 clock periods.

Claim 18

A decoding method for producing a decoded datastream from a received bitstream comprising first, second and third pulse width coded bits representing chances in a single variable parameter of an input datastream said decoding method comprising the steps of generating a first data component representing no change of said parameter, in response to said first coded bit of predetermined duration equal to a multiple of a basic clock period; generating a second data component representing a first type of chance in said parameter, in response to said second coded bit; and generating a third data component representing a second type of change in said parameter, in response to said third coded bit, wherein said first to third pulse width coded bits are different in duration from one another; wherein said first coded bit encompasses N predetermined clock periods; said second coded bit encompasses N+1 clock periods; and said third coded bit encompasses N−1 clock periods.

Claim 19

A decoding method according to claim 13 , further comprising the steps of mixing said received bitstream with a reference signal to produce a frequency downconverted bitstream; frequency demodulating said downconverted bitstream to produce a demodulated signal; and decoding said demodulated signal in accordance with said generating steps to produce said first, second and third data components.

Claim 20

A decoding method according to claim 14 , wherein said mixing step includes the step of phase shifting said received bitstream to produce mutually quadrature phase signals; processing said quadrature signals by means of a spread spectrum demodulator to produce a control signal; and applying said control signal to said mixing step.