← Back to Patent Explorer
US6762445B2 Expired / Lapsed US ⏱️ 0.0 years remaining

DRAM memory cell with dummy lower electrode for connection between upper electrode and upper layer interconnect

Assignee: Panasonic Holdings Corp
•
Filing: 2002-07-17
•
Granted: 2004-07-13
•
Expires: 2022-07-17
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.

Inventors

  • 👤 Hisashi Ogawa
  • 👤 Yoshihiro Mori
  • 👤 Akihiko Tsuzumitani

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 11:12
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/09; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 93 words
A semiconductor memory device, comprising: a memory capacitor that is provided on an insulating layer over a semiconductor substrate and includes by a lower electrode, an upper electrode and a capacitive insulating film interposed between the lower electrode and the upper electrode; an extension of the upper electrode from the upper electrode of the memory capacitor, a dummy conductor member provided such that a part of the dummy conductor member is in contact with an underside of the extension of upper electrode; and upper layer interconnect electrically connected to the dummy conductor member.
Claim 2
Dependent Claim 93 words
A semiconductor memory device, comprising: a memory capacitor that is provided on an insulating layer over a semiconductor substrate and includes by a lower electrode, an upper electrode and a capacitive insulating film interposed between the lower electrode and the upper electrode; an extension of the upper electrode from the upper electrode of the memory capacitor, a dummy conductor member provided such that a part of the dummy conductor member is in contact with an underside of the extension of upper electrode; and upper layer interconnect electrically connected to the dummy conductor member.
Claim 3
Dependent Claim 29 words
The semiconductor memory device according to claim 1 , wherein the dummy conductor member includes a dummy lower electrode formed of the same conductor film as the lower electrode.
Claim 4
Dependent Claim 26 words
The semiconductor memory device according to claim 1 , wherein the dummy conductor member further includes conductor film filling a trench provided in the insulating layer.
Claim 5
Dependent Claim 47 words
The semiconductor memory device according to claim 1 , wherein the dummy conductor member further includes local interconnect provided on the semiconductor substrate under the insulating layer; and a plug piercing through the insulating layer to electrically connect the extension of upper electrode and the local interconnect.
Claim 6
Dependent Claim 38 words
The semiconductor memory device according to claim 4 , further comprising a bit line formed below the memory capacitor across the insulating layer, wherein the local interconnect is formed of the same conductor film as the bit line.
Claim 7
Dependent Claim 29 words
The semiconductor memory device according to claim 4 , wherein at least a part of the extension of upper electrode overlaps the conductor plug when it is viewed two-dimensionally.
Claim 8
Dependent Claim 100 words
The semiconductor memory device according to claim 1 , further comprising: an isolating insulating film provided in a semiconductor substrate below the insulating layer; a memory cell transistor formed in a region of the semiconductor substrate, the memory cell transistor including a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode there between; local interconnect that is provided on the isolating insulating film and is formed of the same conductor film as the gate electrode; and a conductor plug piercing through the insulating layer to connect the local interconnect.
Claim 9
Dependent Claim 83 words
The semiconductor memory device according to claim 1 , further comprising: a memory cell transistor that is provided on the semiconductor substrate and has a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode there between; local interconnect formed of another doped layer that is provided spaced apart from the doped layers on the semiconductor substrate; and a conductor plug piercing through the insulating layer to be connected to the local interconnect.
Claim 10
Dependent Claim 22 words
The semiconductor memory device according to claim 2 , wherein the upper layer interconnect is in contact with the dummy lower electrode.
Claim 11
Dependent Claim 26 words
The semiconductor memory device according to claim 1 , wherein the memory capacitor has a clyndrical lower electrode, a capacitive insulating film and an upper electrode.
Claim 12
Dependent Claim 22 words
The semiconductor memory device according to claim 1 , wherein the capacitive insulating film is a high-κ film or a ferroelectric film.

References Cited (Backward Citations)

US20030052350A1 Cited
US20030015742A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2007-07-13 2008-01-12 2008-07-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2011-07-13 2012-01-12 2012-07-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2015-07-13 2016-01-12 2016-07-13 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag