Duty cycle correction circuit for use with frequency synthesizer

Claim 2

A duty cycle correction circuit for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle, said output pulse signal having the same frequency as that of each of said differential analog signals, said duty cycle correction circuit comprising: a first differential-to-single-ended buffer circuit for processing said pair of differential analog signals into a first digital pulse signal; a second differential-to-single-ended buffer circuit for processing said pair of differential analog signals into a second digital pulse signal, wherein said first digital pulse signal and said second digital pulse signal have a specified phase difference therebetween; a first frequency divider electrically connected with said first differential-to-single-ended buffer circuit for frequency-dividing said first digital pulse signal into a third digital pulse signal; a second frequency divider electrically connected with said second differential-to-single-ended buffer circuit for frequency-dividing said second digital pulse signal into a fourth digital pulse signal; and a symmetrical exclusive OR element electrically connected with said first frequency divider and said second frequency divider for performing an exclusive OR operation so as to produce said output pulse signal.

Claim 3

The duty cycle correction circuit according to claim 1 wherein said specified phase difference is 180 degrees.

Claim 4

The duty cycle correction circuit according to claim 2 wherein said first frequency divider and said second frequency divider respectively include a first divide-by-two circuit and a second divide-by-two circuit.

Claim 5

The duty cycle correction circuit according to claim 1 wherein said symmetrical exclusive OR element includes a first inverter, a second inverter, a first NAND gate, a second NAND gate, and a third NAND gate, wherein an output end of said first inverter is electrically connected with a first input end of said first NAND gate, an output end of said second inverter is electrically connected with a first input end of said second NAND gate, and an output end of said first NAND gate and an output end of said second NAND gate are respectively connected with a first input end and a second input end of said third NAND gate.

Claim 6

The duty cycle correction circuit according to claim 4 wherein said third digital pulse signal is inputted into said first inverter and a second input end of said second NAND gate, and said fourth digital pulse signal is inputted into said second inverter and a second input end of said first NAND gate.

Claim 7

The duty cycle correction circuit according to claim 4 wherein said third NAND gate is a symmetrical NAND gate.

Claim 8

The duty cycle correction circuit according to claim 6 wherein said third NAND gate is implemented by a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, said first PMOS transistor is connected with said first NMOS transistor and said second NMOS transistor in series, said second PMOS transistor is connected with said third NMOS transistor and said fourth NMOS transistor in series, the source terminals of said first PMOS transistor and said second PMOS transistor are connected to a power supply voltage, and the source terminals of said second NMOS transistor and said fourth NMOS transistor are grounded, and wherein the gate terminals of said first PMOS transistor, said first NMOS transistor and said fourth NMOS transistor are interconnected to form said first input end of said third NAND gate; the gate terminals of said second PMOS transistor, said second NMOS transistor and said third NMOS transistor are interconnected to form said second input end of said third NAND gate; and the drain terminals of said first PMOS transistor and said second PMOS transistor are interconnected to form an output end of said third NAND gate.

Claim 9

A frequency synthesizer comprising a control-voltage generating device, an oscillator and a duty cycle correction circuit connected in series, said oscillator delivering a pair of differential analog signals into said duty cycle correction circuit to be converted into an output pulse signal with a duty cycle of substantially 50%, said output pulse signal having the same frequency as that of each of said differential analog signals, said duty cycle correction circuit comprising: a first differential-to-single-ended buffer circuit for processing said pair of differential analog signals into a first digital pulse signal; a second differential-to-single-ended buffer circuit for processing said pair of differential analog signals into a second digital pulse signal, wherein said first digital pulse signal and said second digital pulse signal have a specified phase difference therebetween; a first frequency divider electrically connected with said first differential-to-single-ended buffer circuit for frequency-dividing said first digital pulse signal into a third digital pulse signal; a second frequency divider electrically connected with said second differential-to-single-ended buffer circuit for frequency-dividing said second digital pulse signal into a fourth digital pulse signal; and a symmetrical exclusive OR element electrically connected with said first frequency divider and a said frequency divider for performing an exclusive OR operation so as to produce said output pulse signal.

Claim 10

A frequency synthesizer comprising a control-voltage generating device, an oscillator and a duty cycle correction circuit connected in series, said oscillator delivering a pair of differential analog signals into said duty cycle correction circuit to be converted into an output pulse signal with a duty cycle of substantially 50%, said output pulse signal having the same frequency as that of each of said differential analog signals, said duty cycle correction circuit comprising: a first differential-to-single-ended buffer circuit for processing said pair of differential analog signals into a first digital pulse signal; a second differential-to-single-ended buffer circuit for processing said pair of differential analog signals into a second digital pulse signal, wherein said first digital pulse signal and said second digital pulse signal have a specified phase difference therebetween; a first frequency divider electrically connected with said first differential-to-single-ended buffer circuit for frequency-dividing said first digital pulse signal into a third digital pulse signal; a second frequency divider electrically connected with said second differential-to-single-ended buffer circuit for frequency-dividing said second digital pulse signal into a fourth digital pulse signal; and a symmetrical exclusive OR element electrically connected with said first frequency divider and a said frequency divider for performing an exclusive OR operation so as to produce said output pulse signal.

Claim 11

The frequency synthesizer according to claim 8 wherein said specified phase difference is 180 degrees.

Claim 12

The frequency synthesizer according to claim 9 wherein said first frequency divider and said second frequency divider respectively include a first divide-by-two circuit and a second divide-by-two circuit.

Claim 13

The frequency synthesizer according to claim 8 wherein said symmetrical exclusive OR element includes a first inverter, a second inverter, a first NAND gate, a second NAND gate, and a third NAND gate, wherein an output end of said first inverter is electrically connected with a first input end of said first NAND gate, an output end of said second inverter is electrically connected with a first input end of said second NAND gate, and an output end of said first NAND gate and an output end of said second NAND gate are respectively connected with a first input end and a second input end of said third NAND gate.

Claim 14

The frequency synthesizer according to claim 11 wherein said third digital pulse signal is inputted into said first inverter and a second input end of said second NAND gate, and said fourth digital pulse signal is inputted into said second inverter and a second input end of said first NAND gate.

Claim 15

The frequency synthesizer according to claim 11 wherein said third NAND gate is a symmetrical NAND gate.

Claim 16

The frequency synthesizer according to claim 13 wherein said third NAND gate is implemented by a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, said first PMOS transistor is connected with said first NMOS transistor and said second NMOS transistor in series, said second PMOS transistor is connected with said third NMOS transistor and said fourth NMOS transistor in series, the source terminals of said first PMOS transistor and said second PMOS transistor are connected to a power supply voltage, and the source terminals of said second NMOS transistor and said fourth NMOS transistor are grounded, and wherein the gate terminals of said first PMOS transistor, said first NMOS transistor and said fourth NMOS transistor are interconnected to form said first input end of said third NAND gate; the gate terminals of said second PMOS transistor, said second NMOS transistor and said third NMOS transistor are interconnected to form said second input end of said third NAND gate; and the drain terminals of said first PMOS transistor and said second PMOS transistor are interconnected to form an output end of said third NAND gate.