US6720642B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip chip in leaded molded package and method of manufacture thereof
Assignee: Semiconductor Components Industries LLC
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Filing: 1999-12-16
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Granted: 2004-04-13
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Expires: 2019-12-16
Abstract
Abstract A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
Inventors
- 👤 Rajeev Joshi
- 👤 Consuelo N. Tangpuz
- 👤 Romel N. Manatad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:00
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/481; H10W70/464; H10W70/468; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/131; H10W74/141; H10W46/00; H10W46/101; H10W46/103; H10W46/401; H10W46/601; H10W46/607
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
133 words
A semiconductor die package comprising: a lead frame including a plurality of leads; a semiconductor die including a backside, and source and drain terminals, wherein the backside, and the source and drain terminals are at opposite sides of the semiconductor die, and wherein the semiconductor die is directly coupled to the leadframe using solder; and a molding compound having a window, the molding compound covering at least a portion of the leadframe and at least a portion of the semiconductor die, wherein the plurality of leads extend out of the molding compound and laterally away from the molding compound, and wherein the backside of the semiconductor die is exposed through the window and forms an exterior surface of semiconductor die package and is substantially flush with an exterior surface of the molding compound.
Claim 2
Dependent Claim
133 words
A semiconductor die package comprising: a lead frame including a plurality of leads; a semiconductor die including a backside, and source and drain terminals, wherein the backside, and the source and drain terminals are at opposite sides of the semiconductor die, and wherein the semiconductor die is directly coupled to the leadframe using solder; and a molding compound having a window, the molding compound covering at least a portion of the leadframe and at least a portion of the semiconductor die, wherein the plurality of leads extend out of the molding compound and laterally away from the molding compound, and wherein the backside of the semiconductor die is exposed through the window and forms an exterior surface of semiconductor die package and is substantially flush with an exterior surface of the molding compound.
Claim 3
Dependent Claim
14 words
The semiconductor die package of claim 1 wherein semiconductor die comprises a power transistor.
Claim 4
Dependent Claim
21 words
The semiconductor die package of claim 1 wherein ends of the leads are co-planar with the backside of the semiconductor die.
Claim 5
Dependent Claim
82 words
The semiconductor die package of claim 1 wherein the semiconductor die package further comprises a second semiconductor die including a second backside, and second source and drain terminals, wherein the second semiconductor die is also coupled to the lead frame, and wherein the molding compound has a second window, wherein the second backside is exposed through the second window and forms a second exterior surface of the semiconductor die package and is substantially flush with the exterior surface of the molding compound.
Claim 6
Dependent Claim
30 words
The semiconductor die package of claim 4 wherein the lead frame includes a die attach pad, and wherein the first and second semiconductor dies are on the die attach pad.
Claim 7
Dependent Claim
13 words
The semiconductor die package of claim 1 wherein the lead frame is pre-plated.
Claim 8
Dependent Claim
21 words
The semiconductor die package of claim 6 wherein ends of the leads are co-planar with the backside of the semiconductor die.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-04-13 | 2007-10-13 | 2008-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-04-13 | 2011-10-13 | 2012-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-04-13 | 2015-10-13 | 2016-04-13 | $7700.00 | Window Closed / Lapsed |