Variable transmission rate digital modem with multi-rate filter bank

Claim 2

A digital signal demultiplexer having a band-separation filter bank comprising serially-connected 2-demultiplexing filter banks; wherein a 2-demultiplexing filter bank comprises band-pass filters and down-samplers for culling sampling frequencies of filter output signals to 1/2; and when said 2-demultiplexing filter bank includes four types of filters designated as A, B, C and D in an ascending order in band-pass frequency fs, where fs is a sampling frequency of input signals into each 2-demultiplexing filter bank; then said 2-demultiplexing filter bank is either a first 2-demultiplexing filter bank containing at least filter A or filter B, or a second 2-demultiplexing filter bank containing at least filter C or filter D; and is connected to a next 2-demultiplexing filter bank such that signals processed through said filter A are processed in a next-stage by a first 2-demultiplexing filter bank in said next-stage; signals processed through said filter B are processed in said next-stage by a second 2-demultiplexing filter bank in said next-stage; signals processed through said filter C are processed in said next-stage by another first 2-demultiplexing filter bank in said next-stage; and signals processed through said filter D are processed in said next-stage by another second 2-demultiplexing filter bank in said next-stage.

Claim 3

A digital signal demultiplexer according to claim 1 , wherein signals processed through a filter A are input into a first 2-demultiplexing filter bank or output as signals having a sampling frequency dependent on a number of serially-connected stages in a 2-demultiplexing filter bank containing said filter A; signals processed through a filter B are input into a second 2-demultiplexing filter bank or output as signals having a sampling frequency dependent on a number of serially-connected stages in a 2-demultiplexing filter bank containing said filter B; signals processed through a filter C are input in a first 2-demultiplexing filter bank or output as signals having a sampling speed dependent on a number of serially-connected stages in a 2-demultiplexing filter bank containing said filter C; and signals processed through a filter D are input in a second 2-demultiplexing filter bank or output as signals having a sampling frequency dependent on a number of serially-connected stages in a 2-demultiplexing filter bank containing said filter D.

Claim 4

A digital sender multiplexer having a band-multiplexing filter bank comprising serially-connected 2-multiplexing filter banks; wherein a 2-multiplexing filter bank comprises up-samplers for doubling sampling frequencies of each input signal and filters for filtering output signals from said up-samplers; and adders for multiplexing output signals from each filter when there are two types of said filters; and when said 2-multiplexing filter bank includes four types of filters designated as E, F, G and H in an ascending order in band-pass frequency fs, where fs is a sampling frequency of output signals from each 2-multiplexing filter bank, then 2-multiplexing filter banks are connected such that; signals output from one 2-multiplexing filter bank having at least a filter E or a filter F are input in another 2-multiplexing filter bank having at least a filter E and a filter G; and signals output from one 2-multiplexing filter bank having at least a filter G or a filter H are input into another 2-multiplexing filter bank having at least a filter F or filter H.

Claim 5

A digital sender multiplexer having a band-multiplexing filter bank comprising serially-connected 2-multiplexing filter banks; wherein a 2-multiplexing filter bank comprises up-samplers for doubling sampling frequencies of each input signal and filters for filtering output signals from said up-samplers; and adders for multiplexing output signals from each filter when there are two types of said filters; and when said 2-multiplexing filter bank includes four types of filters designated as E, F, G and H in an ascending order in band-pass frequency fs, where fs is a sampling frequency of output signals from each 2-multiplexing filter bank, then 2-multiplexing filter banks are connected such that; signals output from one 2-multiplexing filter bank having at least a filter E or a filter F are input in another 2-multiplexing filter bank having at least a filter E and a filter G; and signals output from one 2-multiplexing filter bank having at least a filter G or a filter H are input into another 2-multiplexing filter bank having at least a filter F or filter H.

Claim 6

A digital signal multiplexer according to claim 3 , wherein signals input in a 2-multiplexing filter bank comprising either a filter E or a filter G are signals output to another 2-multiplexing filter bank comprised at least by either a filter E or a filter F, or signals having sampling speed dependent on a number of serially-connected stages of 2-multiplexing filter banks comprising either a filter E or a filter G; and input signals to a 2-multiplexing filter bank comprising either a filter F or a filter H are signals output to another 2-multiplexing filter bank comprised at least by either a filter G or a filter H, or signals having sampling speed dependent on a number of serially-connected stages of 2-multiplexing filter banks comprising either a filter F or a filter H.

Claim 7

A digital signal demultiplexer according to claim 1 , wherein a fist-stage of said band-separation filter bank comprises not less than one filter selected from filter A, filter B, filter C and filter D.

Claim 8

A digital signal multiplexer according to claim 3 , wherein a last-stage of said band-multiplexing filter bank comprises not less than one filter selected from filter E, filter F, filter G and filter H.

Claim 9

A digital signal demultiplexer according to claim 1 , wherein said filter A has a lower limit of band-pass frequency of not less than −fs/4 and an upper limit of band-pass frequency of not more than fs/2; said filter B has a lower limit of band-pass frequency of not less than 0 and an upper limit of band-pass frequency of not more than 3fs/4; said filter C has a lower limit of band-pass frequency of not less than −3fs/4 and an upper limit of band-pass frequency of not more than 0; and said filter D has a lower limit of band-pass frequency of not less than −fs/2 and an upper limit of band-pass frequency of not more than fs/4.

Claim 10

A digital signal multiplexer according to claim 3 , wherein said filter E has a lower limit of band-pass frequency of not less than −fs/4 and an upper limit of band-pass frequency of not more than fs/2; said filter F has a lower limit of band-pass frequency of not less than 0 and an upper limit of band-pass frequency of not more than 3fs/4; said filter G has a lower limit of band-pass frequency of not less than −3fs/4 and an upper limit of band-pass frequency of not more than 0; and said filter H has a lower limit of band-pass frequency of not less than −fs/2 and an upper limit of band-pass frequency of not more than fs/4.

Claim 11

A digital signal demultiplexer according to claim 1 , wherein impulse responses A(n), B(n), C(n), D(n) of said filter A, filter B, filter C, filter D, respectively, satisfy equations: I  ( n ) ×  - j   k 4  π   n ,  ( k = 1 , 3 , 5 , 7 ) I  ( n ) = 0   ( n ≠ N 2   and   n   is   an   odd   number ) where n is an integer and 1≦n≦N and I(n) represents an impulse response of a source filter having a tap length N.

Claim 12

A digital signal multiplexer according to claim 3 , wherein impulse responses E(n), F(n), G(n), H(n) of said filter E, filter F, filter G, filter H, respectively, satisfy equations: I  ( n ) ×  - j   k 4  π   n ,  ( k = 1 , 3 , 5 , 7 ) I  ( n ) = 0   ( n ≠ N 2   and   n   is   an   odd   number ) where n is an integer and 1≦n≦N, and I(n) represents an impulse response of a source filter having a tap length N.

Claim 13

A digital signal transmitter comprising: a serial-parallel conversion circuit for converting serial signals into a plurality of parallel slow speed signals; a plurality of modulation circuits for modulating each signal in a plurality of parallel converted signals; a channel multiplexing circuit for frequency multiplexing the modulated signals; where said channel multiplexing circuit comprises not less than one 2-multiplexing filter bank containing: up-samplers for doubling sampling frequencies of each signal in two groups of input signals; two types of filters having different pass-bands for filtering output signals from said up-sampler; and an adder for multiplexing output signals from said two types of filters; and when two or more 2-multiplexing filter banks are required, said channel multiplexing circuit is constructed by serially connecting a plurality of 2-multiplexing filter banks in a multi-stage configuration such that: said plurality of modulation circuits are grouped into groups so that each group contains two modulation circuits, and each two output signals from two modulation circuits of the groups are input into one 2-multiplexing filter bank, respectively; the 2-multiplexing filter banks are grouped into groups so that each group contains two 2-multiplexing filter banks, and each two output signals from the 2-multiplexing filter banks of the groups are further input into another 2-multiplexing filter bank in a next-stage; output signals from two preceding 2-multiplexing filter banks are input into another 2-multiplexing filter bank in a next-stage so that signals from the 2-multiplexing filter bank in a final-stage are produced as output signals from said digital signal transmitter.

Claim 14

A digital signal transmitter comprising: a serial-parallel conversion circuit for converting serial signals into a plurality of parallel slow speed signals; a plurality of modulation circuits for modulating each signal in a plurality of parallel converted signals; a channel multiplexing circuit for frequency multiplexing the modulated signals; where said channel multiplexing circuit comprises not less than one 2-multiplexing filter bank containing: up-samplers for doubling sampling frequencies of each signal in two groups of input signals; two types of filters having different pass-bands for filtering output signals from said up-sampler; and an adder for multiplexing output signals from said two types of filters; and when two or more 2-multiplexing filter banks are required, said channel multiplexing circuit is constructed by serially connecting a plurality of 2-multiplexing filter banks in a multi-stage configuration such that: said plurality of modulation circuits are grouped into groups so that each group contains two modulation circuits, and each two output signals from two modulation circuits of the groups are input into one 2-multiplexing filter bank, respectively; the 2-multiplexing filter banks are grouped into groups so that each group contains two 2-multiplexing filter banks, and each two output signals from the 2-multiplexing filter banks of the groups are further input into another 2-multiplexing filter bank in a next-stage; output signals from two preceding 2-multiplexing filter banks are input into another 2-multiplexing filter bank in a next-stage so that signals from the 2-multiplexing filter bank in a final-stage are produced as output signals from said digital signal transmitter.

Claim 15

A digital signal transmitter according to claim 11 , wherein said channel multiplexing circuit is constructed so that: output signals from one modulation circuit or two modulation circuits are frequency multiplexed by using one of 2-multiplexing filter banks; output signals from said 2-multiplexing filter bank and output signals from one of a plurality of other modulation circuits or output signals fm another 2-multiplexing filter bank having a common sampling rate are frequency multiplexed by using a 2-multiplexing filter bank in a next-stage; and repeating circuit connections further so that signals from a 2-multiplexing filter bank in a final-stage are produced as output signals from said digital signal transmitter.

Claim 16

A digital signal receiver comprising: a plurality of channel demultiplexing circuits for separating frequency multiplexed signals into two groups of signals; a plurality of demodulation circuits for demodulating output signals from said channel demultiplexing circuits; a parallel-serial conversion circuit for receiving output signals from each demodulation circuit; wherein a channel demultiplexing circuit comprises not less than one 2-demultiplexing filter bank having: a circuit for separating input signals into two groups of signals by using two types of filters having different pass-bands; and a down-sampler for culling sampling frequencies of two separated signals to 1/2; and channel demultiplexing circuits are connected such that when there are two or more 2-demultiplexing filter banks, 2-demultiplexing filter banks are connected serially so that output signals from a receiving circuit are input into a 2-demultiplexing filter bank; two groups of signals output from the 2-demultiplexing filter bank are input respectively into 2-demultiplexing filter banks in a next-stage, two groups of signals output from the 2-demultiplexing filter bank are input respectively into 2-demultiplexing filter banks in a next-stage, and ultimately, output signals from the 2-demultiplexing filter banks in a last-stage are input into respective demodulation circuits; and output signals from demodulation circuits are input into said parallel-serial conversion circuit; so that signals output from said parallel-serial conversion circuit are produced as digital receiver output signals.

Claim 17

A digital signal receiver comprising: a plurality of channel demultiplexing circuits for separating frequency multiplexed signals into two groups of signals; a plurality of demodulation circuits for demodulating output signals from said channel demultiplexing circuits; a parallel-serial conversion circuit for receiving output signals from each demodulation circuit; wherein a channel demultiplexing circuit comprises not less than one 2-demultiplexing filter bank having: a circuit for separating input signals into two groups of signals by using two types of filters having different pass-bands; and a down-sampler for culling sampling frequencies of two separated signals to 1/2; and channel demultiplexing circuits are connected such that when there are two or more 2-demultiplexing filter banks, 2-demultiplexing filter banks are connected serially so that output signals from a receiving circuit are input into a 2-demultiplexing filter bank; two groups of signals output from the 2-demultiplexing filter bank are input respectively into 2-demultiplexing filter banks in a next-stage, two groups of signals output from the 2-demultiplexing filter bank are input respectively into 2-demultiplexing filter banks in a next-stage, and ultimately, output signals from the 2-demultiplexing filter banks in a last-stage are input into respective demodulation circuits; and output signals from demodulation circuits are input into said parallel-serial conversion circuit; so that signals output from said parallel-serial conversion circuit are produced as digital receiver output signals.

Claim 18

A digital signal receiver according to claim 13 , wherein said channel demultiplexing circuit is comprised by a serially-connected 2-demultiplexing filter banks, in a multi-stage configuration, and is connected successively so that: input digital signals are input into a 2-demultiplexing filter bank to output two groups of signals, and one group of signals output from the 2-demultiplexing filter bank are input into a 2-demultiplexing filter bank in a next-stage or a demodulation circuit; other group of signals are input into another 2-demultiplexing filter bank in a next-stage or a demodulation circuit; and output signals from a 2-demultiplexing filter bank in a final-stage are input into a final demodulation circuit; so that signals output from said demodulation circuit are input into a parallel-serial conversion circuit.

Claim 19

A digital signal transmitter according to one of claim 11 , wherein said serial-parallel conversion circuit is a multi-input/output serial-parallel conversion circuit for converting input signals into a plurality of slow speed signals.

Claim 20

A digital signal transmitter according to claim 12 , wherein said serial-parallel conversion circuit is a multi-input/output serial-parallel conversion circuit for converting input signals into a plurality of slow speed signals.

Claim 21

A digital signal receiver according to claim 13 , wherein said parallel-serial conversion circuit is a multi-input/output parallel-serial conversion circuit for receiving output signals from each demodulation circuit.

Claim 22

A digital signal receiver according to claim 14 , wherein said parallel-serial conversion circuit is a multi-input/output parallel-serial conversion circuit for receiving output signals from each demodulation circuit.

Claim 23

A digital signal receiver according to claim 17 , wherein said receiver is further provided with a modulation circuit for modulating a plurality of output signals from said multi-input/output parallel-serial conversion circuit.

Claim 24

A digital signal receiver according to claim 18 , wherein said receiver is further provided with a modulation circuit for modulating a plurality of output signals from said multi-input/output parallel-serial conversion circuit.

Claim 25

A digital signal transmitter according to claim 11 , wherein said modulation circuit and at least a part of said channel multiplexing circuit are operated in a time-division mode.

Claim 26

A digital signal transmitter according to claim 12 , wherein said modulation circuit and at least a part of said channel multiplexing circuit are operated in a time-division mode.

Claim 27

A digital signal transmitter according to claim 15 , wherein said modulation circuit and at least a part of said channel multiplexing circuit are operated in a time-division mode.

Claim 28

A digital signal receiver according to claim 13 , wherein said demodulation circuit and at least a part of said channel demultiplexing circuit are operated in a time-division mode.

Claim 29

A digital signal receiver according to claim 14 , wherein said demodulation circuit and at least a part of said channel demultiplexing circuit are operated in a time-division mode.

Claim 30

A digital signal receiver according to claim 17 , wherein said demodulation circuit and at least a part of said channel demultiplexing circuit are operated in a time-division mode.

Claim 31

A digital signal receiver according to claim 19 , wherein said demodulation circuit and at least a part of said channel demultiplexing circuit are operated in a time-division mode.

Claim 32

A digital signal transmitter according to claim 12 , wherein a plurality of slow speed signals has different speeds.

Claim 33

A digital signal receiver according to claim 14 , wherein a plurality of slow speed signals has different speeds.

Claim 34

A digital signal transmitter according to claim 12 , wherein 2-multiplexing filter banks in a channel multiplexing circuit are connected so as to enable to operate when signal speeds of slow speed signal input in said channel multiplexing circuit are all different.

Claim 35

A digital signal receiver according to claim 14 , wherein 2-demultiplexing filter banks in a channel demultiplexing circuit are connected so as to enable to operate when signal speeds of slow speed signal input in said channel demultiplexing circuit are all different.

Claim 36

A digital modem comprising a digital signal transmitter according to claim 11 and a digital signal receiver according to claim 13 .

Claim 37

A digital modem comprising a digital signal receiver according to claim 13 .