US6687844B1
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Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal
Assignee: Intel Corp
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Filing: 2000-09-28
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Granted: 2004-02-03
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Expires: 2020-09-28
Abstract
Abstract A device and method to detect and correct clock duty cycle skew detected in high performance microprocessor having a very high frequency clock. The device relies on a delay chain circuit to delay the clock signal and determine the presence of clock duty cycle skew. The device uses simple latches, flops and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is then employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of uniform time duration.
Inventors
- 👤 Binglong Zhang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:58
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
152 words
A method of correcting clock duty cycle skew, comprising: generating a clock signal having clock cycles; delaying the clock signal by a clock cycle to generate a delayed clock signal; measuring the time interval between a phase 1 clock cycle and a phase 2 clock cycle in the clock signal and storing it as a first time period; measuring the time interval between the phase 2 clock cycle and a second phase 1 clock cycle in the clock signal and storing it as a second time period; determining when a delayed phase 2 clock cycle of the delayed clock cycle is high; subtracting the first time interval from the second time interval to yield a third time interval; and adjusting the start of the delayed phase 2 clock cycle by half of the third time interval so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.
Claim 2
Independent Claim
152 words
A method of correcting clock duty cycle skew, comprising: generating a clock signal having clock cycles; delaying the clock signal by a clock cycle to generate a delayed clock signal; measuring the time interval between a phase 1 clock cycle and a phase 2 clock cycle in the clock signal and storing it as a first time period; measuring the time interval between the phase 2 clock cycle and a second phase 1 clock cycle in the clock signal and storing it as a second time period; determining when a delayed phase 2 clock cycle of the delayed clock cycle is high; subtracting the first time interval from the second time interval to yield a third time interval; and adjusting the start of the delayed phase 2 clock cycle by half of the third time interval so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.
Claim 3
Dependent Claim
37 words
The method recited in claim 1 , further comprises: controlling the operation of a microprocessor using the delayed clock signal adjusted so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.
Claim 4
Dependent Claim
37 words
The method recited in claim 1 , wherein the adjusting of the start of the delayed phase 2 clock cycle further comprises: determining the direction of adjustment of the start of the delayed phase 2 clock cycle.
Claim 5
Dependent Claim
66 words
The method recited in claim 3 , wherein the direction of adjustment of the start of the delayed phase 2 clock cycle causes the start of delayed phase 2 clock cycle to be delayed by half of the third time interval when a phase 1 cycle of the clock signal has a value equal to high at the same time as the delayed phase clock cycle.
Claim 6
Dependent Claim
67 words
The method recited in claim 3 , wherein the direction of adjustment of the start of the delayed phase 2 clock cycle causes the start of delayed phase 2 clock cycle to be earlier by half of the third time interval when a phase 1 cycle of the clock signal has a value equal to opposite that of the delayed phase clock cycle at the same time.
Claim 7
Dependent Claim
68 words
The method recited in claim 4 , wherein the third interval value is determined by increasing the delay of the delayed clock signal until phase 1 clock cycle and delayed phase 2 clock cycle have opposite values to one another, and the delay of the delayed clock signal is incrementally increased until the phase 1 clock cycle and the delayed phase 2 clock cycle have the same value.
Claim 8
Dependent Claim
70 words
The method recited in claim 5 , wherein the third interval value is determined by decreasing the delay of the delayed clock signal until phase 1 clock cycle and delayed phase 2 clock cycle have opposite values to one another, and the delay of the delayed clock signal is incrementally decreased until the phase 1 clock cycle and the delayed phase 2 clock cycle do not have the same value.
Claim 9
Independent Claim
203 words
A device to correct clock duty cycle skew, comprising: a delay chain circuit to delay a clock signal and generate a delayed clock signal; a phase detector connected to the delay chain circuit to receive and compare the clock signal and delayed clock signal, wherein the phase detector will output a value of one or high when a leading edge of a clock cycle from the clock signal and a leading edge of a delayed clock cycle of the delayed clock signal are both high or equal to 1; a first latch connected to the clock signal and the phase detector to receive the clock signal and the output from the phase detector and generate a value of 1 or high; an inverter connected to the clock signal to clip of the value of the clock signal; a second latch connected to the inverter and the phase detector to receive the clock signal and the output from the phase detector and generate a value of 1 or high; and a skew logic unit connected to the first latch and the second latch to identify the presence of skew in the clock signal and adjust the delayed clock signal to compensate for the skew.
Claim 10
Independent Claim
203 words
A device to correct clock duty cycle skew, comprising: a delay chain circuit to delay a clock signal and generate a delayed clock signal; a phase detector connected to the delay chain circuit to receive and compare the clock signal and delayed clock signal, wherein the phase detector will output a value of one or high when a leading edge of a clock cycle from the clock signal and a leading edge of a delayed clock cycle of the delayed clock signal are both high or equal to 1; a first latch connected to the clock signal and the phase detector to receive the clock signal and the output from the phase detector and generate a value of 1 or high; an inverter connected to the clock signal to clip of the value of the clock signal; a second latch connected to the inverter and the phase detector to receive the clock signal and the output from the phase detector and generate a value of 1 or high; and a skew logic unit connected to the first latch and the second latch to identify the presence of skew in the clock signal and adjust the delayed clock signal to compensate for the skew.
Claim 11
Dependent Claim
49 words
The device recited in claim 8 , wherein the first latch will output a value of one or high when the leading edge of a phase 1 clock cycle of the clock signal matches the leading edge of a delayed phase 2 clock cycle of the delayed clock signal.
Claim 12
Dependent Claim
49 words
The device recited in claim 9 , wherein the second latch will output a value of one or high when the leading edge of a phase 2 clock cycle of the clock signal matches the leading edge of a delayed phase 1 clock cycle of the delayed clock signal.
Claim 13
Dependent Claim
49 words
The device recited in claim 10 , wherein the skew logic unit will determine a first time interval based on detection of the leading edge of the phase 1 clock cycle of the clock signal and the leading edge of the phase 2 clock cycle of the clock signal.
Claim 14
Dependent Claim
50 words
The device recited in claim 11 , wherein the skew logic unit will determine a second time interval based on detection of the leading edge of the phase 2 clock cycle of the clock signal and the leading edge of a second phase 1 clock cycle of the clock signal.
Claim 15
Dependent Claim
29 words
The device recited in claim 12 , wherein the skew logic unit will determine a third time interval by subtracting the first time interval from the second time interval.
Claim 16
Dependent Claim
64 words
The device recited in claim 13 , wherein the skew logic unit will determine a direction of adjustment of the start of the delayed phase 2 clock cycle to be earlier by half of the third time interval when a phase 1 cycle of the clock signal has a value equal to opposite that of the delayed phase clock cycle at the same time.
Claim 17
Dependent Claim
73 words
The device recited in claim 14 , wherein the skew logic unit determines the third interval value by increasing the delay of the delayed clock signal until the phase 1 clock cycle and the delayed phase 2 clock cycle have opposite values to one another, and the delay of the delayed clock signal is incrementally increased until the phase 1 clock cycle and the delayed phase 2 clock cycle have the same value.
Claim 18
Dependent Claim
75 words
The device recited in claim 14 , wherein the skew logic unit determines the third interval value is determined by decreasing the delay of the delayed clock signal until phase 1 clock cycle and delayed phase 2 clock cycle have opposite values to one another, and the delay of the delayed clock signal is incrementally decreased until the phase 1 clock cycle and the delayed phase 2 clock cycle do not have the same value.
Claim 19
Dependent Claim
147 words
A computer program, comprising: monitoring a clock signal having clock cycles; delaying the clock signal by a clock cycle to generate a delayed clock signal; measuring the time interval between a phase 1 clock cycle and a phase 2 clock cycle in the clock signal and storing it as a first time period; measuring the time interval between the phase 2 clock cycle and a second phase 1 clock cycle in the clock signal and storing it as a second time period; determining when a delayed phase 2 clock cycle of the delayed clock cycle is high; subtracting the first time interval from the second time interval to yield a third time interval; and adjusting the start of the delayed phase 2 clock cycle by half of the third time interval so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.
Claim 20
Dependent Claim
147 words
A computer program, comprising: monitoring a clock signal having clock cycles; delaying the clock signal by a clock cycle to generate a delayed clock signal; measuring the time interval between a phase 1 clock cycle and a phase 2 clock cycle in the clock signal and storing it as a first time period; measuring the time interval between the phase 2 clock cycle and a second phase 1 clock cycle in the clock signal and storing it as a second time period; determining when a delayed phase 2 clock cycle of the delayed clock cycle is high; subtracting the first time interval from the second time interval to yield a third time interval; and adjusting the start of the delayed phase 2 clock cycle by half of the third time interval so that the intervals between delayed clock cycles in delayed clock signal are of equal duration.
Claim 21
Dependent Claim
38 words
The computer program recited in claim 17 , wherein the adjusting of the start of the delayed phase 2 clock cycle further comprises: determining the direction of adjustment of the start of the delayed phase 2 clock cycle.
Claim 22
Dependent Claim
67 words
The computer program recited in claim 18 , wherein the direction of adjustment of the start of the delayed phase 2 clock cycle causes the start of delayed phase 2 clock cycle to be delayed by half of the third time interval when a phase 1 cycle of the clock signal has a value equal to high at the same time as the delayed phase clock cycle.
Claim 23
Dependent Claim
68 words
The computer program recited in claim 18 , wherein the direction of adjustment of the start of the delayed phase 2 clock cycle causes the start of delayed phase 2 clock cycle to be earlier by half of the third time interval when a phase 1 cycle of the clock signal has a value equal to opposite that of the delayed phase clock cycle at the same time.
Claim 24
Dependent Claim
69 words
The computer program recited in claim 19 , wherein the third interval value is determined by increasing the delay of the delayed clock signal until phase 1 clock cycle and delayed phase 2 clock cycle have opposite values to one another, and the delay of the delayed clock signal is incrementally increased until the phase 1 clock cycle and the delayed phase 2 clock cycle have the same value.
Claim 25
Dependent Claim
71 words
The computer program recited in claim 20 , wherein the third interval value is determined by decreasing the delay of the delayed clock signal until phase 1 clock cycle and delayed phase 2 clock cycle have opposite values to one another, and the delay of the delayed clock signal is incrementally decreased until the phase 1 clock cycle and the delayed phase 2 clock cycle do not have the same value.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-02-02 | 2007-08-04 | 2008-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-02-02 | 2011-08-04 | 2012-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-02-02 | 2015-08-04 | 2016-02-03 | $7700.00 | Window Closed / Lapsed |