Nonvolatile flash memory device usable as boot-up memory in a digital information processing system and method of operating the same

Claim 2

A flash memory device comprising: a plurality of nonvolatile memory cells; a power detecting circuit to generate a first detection signal when a power supply voltage is lower than a predetermined detection voltage; address generator to generate an address responsive to the first detection signal of the power detecting circuit; a read circuit to read data from the plurality of nonvolatile memory cells in response to the generated address; and a control circuit to control activation of the read circuit dependent on predetermined device information when the power supply voltage is lower than the predetermined detection voltage.

Claim 3

The flash memory device according to claim 1 , in which the power detecting circuit uses an internal supply voltage of the memory device for the detection voltage, internal supply voltage being lower than the power supply voltage.

Claim 4

The flash memory device according to claim 1 , in which the power detecting circuit uses as the detection voltage, a signal established with a level lower than the power supply voltage and greater than an internal supply voltage of the memory device, the internal supply voltage to be lower than the power supply voltage.

Claim 5

The flash memory device according to claim 1 , in which the power detecting circuit comprises a transistor of threshold voltage to establish the detection voltage with a level lower than an internal supply voltage of the memory device, the internal supply voltage to be lower than the power supply voltage.

Claim 6

The flash memory device according to claim 1 , in which the address generator includes an address buffer to store an address externally applied thereto.

Claim 7

The flash memory device according to claim 1 , in which the device information is to indicate whether or not the memory device is to be used as a boot-up memory.

Claim 8

The flash memory device according to claim 1 , in which the control circuit includes a programmable element to store the device information.

Claim 9

The flash memory device according to claim 7 , in which the programmable element is to store device information to indicate whether or not the memory device is to be used as a boot-up memory.

Claim 10

The flash memory device according to claim 1 , in which the control circuit comprises a pad formed on the memory device, the pad being electrically coupled to one of a first device setting voltage or a second device setting voltage.

Claim 11

The flash memory device according to claim 9 , wherein the pad is one of pads to interface the memory device with external circuits.

Claim 12

The flash memory device according to claim 9 , wherein the pad comprises a bonding pad.

Claim 13

The flash memory device according to claim 9 , wherein one of the first and second device setting voltages comprises a logic zero voltage and the other, a logic one voltage.

Claim 14

The flash memory device according to claim 1 , in which the control circuit includes a fuse circuit having at least one fuse, the fuse circuit to selectively provide either a first device setting voltage or a second device setting voltage dependent on a connection state of the at least one fuse.

Claim 15

The flash memory device according to claim 13 , wherein one of the first and second device setting voltages is a logic zero voltage and the other is a logic one voltage.

Claim 16

A flash memory device comprising: a memory cell array having a plurality of nonvolatile memory cells arranged in rows and columns; a power detecting circuit to generate a first detection signal when a power supply voltage is lower than a predetermined detection voltage; address generating means for internally generating an address in response to the first detection signal; a read circuit to read data from the memory cell array dependent on internally generated addresses of the address generating means; and a control circuit to generate a control signal to control the read circuit dependent on device information and whether or not the power supply voltage is lower than a predetermined detection voltage; wherein the read circuit comprises: a row selecting circuit to select one or more rows of the memory cell array dependent on a row address of the internally generated address; a column selecting circuit to select one or more columns of the memory cell array dependent on a column address of the internally generated address; a page buffer circuit to sense data from selected memory cells of the selected columns; a read initiate circuit to generate a second detection signal when the power supply voltage reaches the predetermined detection voltage and the control signal is active; and a read controller to control a sensing operation of the page buffer circuit responsive to the second detection signal; and wherein the read initiate circuit is to be selectively controlled by the control signal of the control circuit based upon the device information and whether or not the power supply voltage is lower than the predetermined detection voltage.

Claim 17

A flash memory device comprising: a memory cell array having a plurality of nonvolatile memory cells arranged in rows and columns; a power detecting circuit to generate a first detection signal when a power supply voltage is lower than a predetermined detection voltage; address generating means for internally generating an address in response to the first detection signal; a read circuit to read data from the memory cell array dependent on internally generated addresses of the address generating means; and a control circuit to generate a control signal to control the read circuit dependent on device information and whether or not the power supply voltage is lower than a predetermined detection voltage; wherein the read circuit comprises: a row selecting circuit to select one or more rows of the memory cell array dependent on a row address of the internally generated address; a column selecting circuit to select one or more columns of the memory cell array dependent on a column address of the internally generated address; a page buffer circuit to sense data from selected memory cells of the selected columns; a read initiate circuit to generate a second detection signal when the power supply voltage reaches the predetermined detection voltage and the control signal is active; and a read controller to control a sensing operation of the page buffer circuit responsive to the second detection signal; and wherein the read initiate circuit is to be selectively controlled by the control signal of the control circuit based upon the device information and whether or not the power supply voltage is lower than the predetermined detection voltage.

Claim 18

The flash memory device according to claim 15 , wherein the address generating means comprises an address buffer to store an address externally applied thereto.

Claim 19

The flash memory device according to claim 15 , in which the control circuit comprises a storage circuit to store the device information.

Claim 20

The flash memory device according to claim 17 , the control circuit to use the device information to determine whether or not the memory device is to be used as a boot-up memory.

Claim 21

The flash memory device according to claim 18 , the storage circuit to include a pad formed on the memory device, the pad to be connected to one of either a first device setting voltage or a second device setting voltage.

Claim 22

The flash memory device according to claim 19 , in which the pad is one of several pads operable to interface external devices.

Claim 23

The flash memory device according to claim 19 , in which the pad comprises a bonding pad.

Claim 24

The flash memory device according to claim 19 , in which one of the first and second device setting voltages is the power supply voltage and the other is a ground voltage.

Claim 25

The flash memory device according to claim 18 , in which the storage circuit comprises a fuse circuit having at least one fuse, the fuse operable to provide the fuse circuit with one of a first device setting voltage or a second device setting voltage based on the connection state of the at least one fuse.

Claim 26

The flash memory device according to claim 23 , in which one of the first and second device setting voltages is the power supply voltage and the other is a ground voltage.

Claim 27

A flash memory device comprising: a plurality of nonvolatile memory cells arranged in rows and columns; a detector to generate a first detection signal when a power supply voltage is lower than a predetermined threshold; addressor to internally generate an address responsive to the first detection signal of the detector; a read circuit to read data of the plurality of memory cells responsive to an internally generated address of the addressor; and a controller to determine device information and to check a level of the power supply voltage; the controller operable to control the read circuit based upon its device information determination and the supply level check; and the power detecting circuit to be activated selectively under the control of the control circuit based upon the device information determination and the level check.

Claim 28

A flash memory device comprising: a plurality of nonvolatile memory cells arranged in rows and columns; a detector to generate a first detection signal when a power supply voltage is lower than a predetermined threshold; addressor to internally generate an address responsive to the first detection signal of the detector; a read circuit to read data of the plurality of memory cells responsive to an internally generated address of the addressor; and a controller to determine device information and to check a level of the power supply voltage; the controller operable to control the read circuit based upon its device information determination and the supply level check; and the power detecting circuit to be activated selectively under the control of the control circuit based upon the device information determination and the level check.

Claim 29

The flash memory device according to claim 25 , in which: the controller is operable to determine when the level of the power supply voltage drops below the predetermined threshold; the controller is to control the read circuit dependent upon determining that the power supply voltage is below the predetermined threshold; and the power detecting circuit to be activated selectively under the control of the control circuit based upon the device information determination and when the level of the power supply voltage is determined to be below the predetermined threshold.

Claim 30

The flash memory device according to claim 25 , in which the read circuit comprises: a row selecting circuit to select one or more rows based on a row address of an internally generated address of the addressor; a column selecting circuit to select one or more columns based on a column address of an internally generated address of the addressor; a page buffer circuit to sense data stored in memory cells of the selected columns; a read initiate circuit to generate a second detection signal when the power supply voltage reaches the predetermined detection voltage and a control signal of the controller is active; and a read controller to control a sense operation of the page buffer circuit responsive to the second detection signal of the read initiate signal.

Claim 31

The flash memory device according to claim 25 , in which the addressor comprises an address buffer to store an address externally applied thereto.

Claim 32

The flash memory device according to claim 25 , in which the controller comprises a storage circuit to store the device information.

Claim 33

The flash memory device according to claim 29 , in which the controller is to determine whether or not to enable use of the memory device as a boot-up memory based on the device information.

Claim 34

The flash memory device according to claim 30 , in which the storage circuit includes a pad of the memory device, the pad being connected to one of a first device setting voltage or a second device setting voltage.

Claim 35

The flash memory device according to claim 31 , in which the pad is one of a plurality of pads to interface the memory device to external devices.

Claim 36

The flash memory device according to claim 31 , in which the pad comprises a bonding pad.

Claim 37

The flash memory device according to claim 31 , in which one of the first and second device setting voltages is the power supply voltage and the other is a ground voltage.

Claim 38

The flash memory device according to claim 30 , in which the storage circuit comprises a fuse operable to establish the device information based on a connection state thereof.

Claim 41

The method according to claim 36 , in which the determining comprises reading device information that may indicate whether or not the memory device is to be set as the boot-up memory when a power supply voltage is determined lower than a predetermined detection voltage.

Claim 42

The method according to claim 37 , in which the reading boot-up data comprises: generating an address internally when the device information indicates the memory device to be set as a boot-up memory; and sensing the boot-up data of the memory dependent on the internally generated address when the power supply voltage reaches the predetermined detection voltage.

Claim 43

The method according to claim 38 , further comprising preventing the sensing when the device information indicates the memory device is not to be set as the boot-up memory.