Fringe field switching mode LCD

Claim 2

A fringe field switching mock LCD comprising: a first transparent insulating substrate; a second transparent insulating substrates arranged opposite to the first substrate at a distance; a liquid crystal layer having liquid crystal molecules interposed between the first and second substrates; a plurality of gate bus lines and a plurality of data bus lines formed on the first substrate, wherein an area formed by two gate bus lines intersecting two data bus lines substantially defines a unit pixel; a thin film transistor formed at a selected intersection of the gate bus line and the data bus line; a counter electrode made from a transparent conductor material disposed in each unit pixel; and a pixel electrode also made from a transparent conductor material arranged in each unit pixel and insulated from the counter electrode of the same unit pixel to generate a fringe field in the liquid crystal layer in cooperation with the counter electrode, wherein the pixel electrode has a plurality of upper slits parallelly arranged at a first tilt angle in a portion of the unit pixel and a plurality of lower slits parallelly arranged at a second tilt angle in another portion of the unit pixel, wherein the upper slits and the lower slits are arranged in the unit pixel as minor images of each other such that the first and second tilt angles are measured with respect to the axis that divides the upper and lower slits into mirror images, and further wherein no upper slit is connected to any of the lower slits.

Claim 3

The fringe field switching mode LCD according to claim 1 , wherein the pixel electrode further comprises a reference slit dividing the upper slit and the lower slit and arranged parallel to the gate bus line.

Claim 4

The fringe field switching mode LCD according to claim 1 , wherein the first tilted angle of the upper slits and the second tilt angle of the lower slits are between +45 degree and −45 degree.

Claim 5

The fringe field switching mode LCD according to claim 3 , wherein the first tilted angle of the upper slits and the second tilt angle of the lower slits are between −2 degree and about +20 degree.

Claim 6

The fringe field switching mode LCD according to claim 1 , wherein the width of each of the upper or lower slit is between −1 μm and about +8 μm and the distance between two adjacent slits is between −1 μm and about +8 μm.

Claim 7

The fringe field switching mode LCD according to claim 1 , wherein the slits of the pixel electrode in one unit pixel and the slits of the pixel electrode in an adjacent unit pixel are arranged as mirror images of each other.

Claim 8

The fringe field switching mode LCD according to claim 1 , further comprising a first alignment layer arranged between the first substrate and the liquid crystal layer; a second alignment layers arranged between the liquid crystal layer and the second substrate; a first polarizing plate arranged on the outer side of the first substrate; and a second polarizing plates arranged on outer side of the second substrates.

Claim 9

The fringe field switching mode LCD according to claim 7 , wherein the first and the second alignment layers are rubbed parallel to the gate bus line when liquid crystals are anisotropically positive or parallel to the data bus line when the liquid crystals are anisotropically negative.

Claim 10

The fringe field switching mode LCD according to claim 7 , wherein the first polarizing plate has a first transmission axis and the second polarizing plate has a second transmission axis, wherein the first and second transmission axes are perpendicular to each other and one of the axes is in the same direction as the rubbing direction of the alignment layer.

Claim 11

The fringe field switching mode LCD according to claim 1 , further comprising a common electrode line for providing common signals to the counter electrode.

Claim 12

The fringe field switching mode LCD according to claim 10 , wherein the common electrode line is arranged on the edge of the unit pixel adjacent the gate bus line, parallel to the gate bus line.

Claim 13

The fringe field switching mode LCD according to claim 10 , wherein the common electrode line is arranged on a line along the center of the unit pixel, parallel to the gate bus line.

Claim 14

A fringe filed switching mode LCD comprising: a first transparent insulating substrate; and a second transparent insulating substrates arranged opposite to the first substrate at a distance; a liquid crystal layer having liquid crystal molecules interposed between the first and second substrates; a plurality of gate bus lines and a plurality of data bus lines formed on the first substrate, wherein an area formed by two gate bus lines intersecting two data bus lines substantially defines a unit pixel; a thin film transistor formed at a selected intersection of the gate bus line and the data bus line; a counter electrode made from a transparent conductor material disposed in each unit pixel; a pixel electrode also made from a transparent conductor material arranged in each unit pixel and insulated from the counter electrode to generate a fringe field in the liquid crystal layer, wherein the pixel electrode has a plurality of upper slits parallely arranged at a first tilt angle in a portion of the unit pixel and a plurality of lower slits parallely arranged at a second tilt angle in another portion of the unit pixel. wherein the upper slits and the lower slits are arranged in the unit pixel as mirror images of each other such that the tilt angle is measured with respect to the axis that divides the upper and lower slits into mirror images, and further wherein no upper slit is connected to any of the lower slit; a first alignment layer arranged between the first substrate and the liquid crystal layer; a second alignment layers arranged between the liquid crystal layer and the second substrates; a first polarizing plate arranged on the outer side of the first substrate; and a second polarizing plates arranged on the outer sides of the second substrates.

Claim 15

A fringe filed switching mode LCD comprising: a first transparent insulating substrate; and a second transparent insulating substrates arranged opposite to the first substrate at a distance; a liquid crystal layer having liquid crystal molecules interposed between the first and second substrates; a plurality of gate bus lines and a plurality of data bus lines formed on the first substrate, wherein an area formed by two gate bus lines intersecting two data bus lines substantially defines a unit pixel; a thin film transistor formed at a selected intersection of the gate bus line and the data bus line; a counter electrode made from a transparent conductor material disposed in each unit pixel; a pixel electrode also made from a transparent conductor material arranged in each unit pixel and insulated from the counter electrode to generate a fringe field in the liquid crystal layer, wherein the pixel electrode has a plurality of upper slits parallely arranged at a first tilt angle in a portion of the unit pixel and a plurality of lower slits parallely arranged at a second tilt angle in another portion of the unit pixel. wherein the upper slits and the lower slits are arranged in the unit pixel as mirror images of each other such that the tilt angle is measured with respect to the axis that divides the upper and lower slits into mirror images, and further wherein no upper slit is connected to any of the lower slit; a first alignment layer arranged between the first substrate and the liquid crystal layer; a second alignment layers arranged between the liquid crystal layer and the second substrates; a first polarizing plate arranged on the outer side of the first substrate; and a second polarizing plates arranged on the outer sides of the second substrates.