← Back to Patent Explorer
US6645010B1 Expired / Lapsed US ⏱️ 0.0 years remaining

High density electrical connector with improved grounding bus

Assignee: Hon Hai Precision Industry Co Ltd
•
Filing: 2002-06-07
•
Granted: 2003-11-11
•
Expires: 2022-06-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An electrical connector ( 1 ) comprises a dielectric frame ( 10 ) defining a receiving cavity ( 12 ), a plurality of printed circuit substrates ( 30 ), and a spacer ( 20 ) assembled with the printed circuit substrates. The spacer includes a plurality of wafers ( 21 ) and defines a plurality of tunnels ( 22 ) between every two adjacent wafers for receiving corresponding printed circuit substrates. Each wafer has a dielectric body ( 23 ), a plurality of terminals ( 25 ) for conductively contacting signal traces of the printed circuit substrate, and a grounding bus ( 24 ) covering on the dielectric body. Each grounding bus forms at least one resilient arm ( 28 ) conductively contacting with grounding traces on the printed circuit substrate before the signal terminals conductively contact the signal traces on the printed circuit substrate.

Inventors

  • 👤 Timothy B. Billman
  • 👤 Iosif R. Korsunsky

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 10:29
CPC Classifications
H; H01; H01R; H01R13/00; H01R13/648; H01R13/658; H01R13/6581; H01R13/6585; H01R13/6586; H01R13/6587

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 338 words
An electrical connector comprising: a dielectric frame defining a receiving cavity; and a spacer received in the receiving cavity, the spacer including a plurality of wafers defining a plurality of tunnels between every two adjacent wafers for accommodating printed circuit substrates therein, each wafer having a dielectric body, a plurality of signal terminals retained in the dielectric body, each signal terminal forming a contact point for conductively contacting a signal trace formed on a corresponding printed circuit substrate, and a grounding bus covering the dielectric body and having at least one resilient arm having an arc free end for conductively contacting with a grounding trace formed on the corresponding printed circuit substrate; wherein the arc free end of the at least one resilient arm is located higher than the contact point of each signal terminal so that the at least resilient arm conductively contact with the grounding trace before the signal terminals conductively contact with the signal traces of the corresponding printed circuit substrate; wherein the grounding bus has a body plate covering a side surface of the dielectric body of each wafer; wherein the grounding bus has a pair of resilient arms extending upwardly and convergently from opposite sides of the body plate of the grounding bus; wherein each resilient arm forms an arc free end extending out of another side surface opposite to the side surface of the dielectric body for conductively contacting the grounding trace of the corresponding printed circuit substrate; wherein the arc free ends of the resilient arms are located higher than the contact points of the signal terminals and thus adapted to firstly conductively contact the grounding trace of the corresponding printed circuit substrate before the contact points of the signal terminals are adapted to conductively contact the signal trace of the corresponding printed circuit substrate; wherein the body plate of the grounding bus further forms a plurality of resilient ribs for electrically connecting with the corresponding printed circuit substrate and a plurality of grounding tails for insertion into a circuit board.
Claim 2
Dependent Claim 338 words
An electrical connector comprising: a dielectric frame defining a receiving cavity; and a spacer received in the receiving cavity, the spacer including a plurality of wafers defining a plurality of tunnels between every two adjacent wafers for accommodating printed circuit substrates therein, each wafer having a dielectric body, a plurality of signal terminals retained in the dielectric body, each signal terminal forming a contact point for conductively contacting a signal trace formed on a corresponding printed circuit substrate, and a grounding bus covering the dielectric body and having at least one resilient arm having an arc free end for conductively contacting with a grounding trace formed on the corresponding printed circuit substrate; wherein the arc free end of the at least one resilient arm is located higher than the contact point of each signal terminal so that the at least resilient arm conductively contact with the grounding trace before the signal terminals conductively contact with the signal traces of the corresponding printed circuit substrate; wherein the grounding bus has a body plate covering a side surface of the dielectric body of each wafer; wherein the grounding bus has a pair of resilient arms extending upwardly and convergently from opposite sides of the body plate of the grounding bus; wherein each resilient arm forms an arc free end extending out of another side surface opposite to the side surface of the dielectric body for conductively contacting the grounding trace of the corresponding printed circuit substrate; wherein the arc free ends of the resilient arms are located higher than the contact points of the signal terminals and thus adapted to firstly conductively contact the grounding trace of the corresponding printed circuit substrate before the contact points of the signal terminals are adapted to conductively contact the signal trace of the corresponding printed circuit substrate; wherein the body plate of the grounding bus further forms a plurality of resilient ribs for electrically connecting with the corresponding printed circuit substrate and a plurality of grounding tails for insertion into a circuit board.

References Cited (Backward Citations)

US6083047A Cited
US5980321A Cited
US6152747A Cited
US6174202B1 Cited
US6299484B2 Cited
US6171115B1 Cited
US6267604B1 Cited
US6390857B1 Cited
US6375508B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-11-10 2007-05-12 2007-11-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-11-10 2011-05-12 2011-11-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-11-10 2015-05-12 2015-11-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag