Photo mask pattern designing method, resist pattern fabricating method and semiconductor device manufacturing method

Claim 2

A photo mask pattern designing method configured to correct pattern configuration of at least one of a plurality of kinds of photo masks for making a single-layered resist pattern by transferring pattern configuration by use of multiple exposures of a resist coated on a substrate, characterized in that: a first photo mask used for exposure using interference of light from said multiple exposures has a first shading region and a first translucent region adjacent to each other; a second photo mask used for exposure before or after said exposure using interference of light has a second shading region and a second translucent region adjacent to each other; said first shading region and said second shading region are substantially aligned in location in said first photo mask and said second photo mask; said first translucent region and said second translucent region are substantially aligned in location in said first photo mask and said second photo mask; said first shading region is corrected in width in the direction of adjacent alignment of said first shading region and said first translucent region; and said second shading region is corrected in width in the direction of adjacent alignment of said second shading region and said second translucent region.

Claim 3

The photo mask pattern designing method according to claim 1 wherein correction of said second shading region in said second photo mask is preferentially conducted.

Claim 4

The photo mask pattern designing method according to claim 1 wherein said first photo mask is a phase shift mask.

Claim 5

The photo mask pattern designing method according to claim 1 wherein said second photo mask is a binary mask.

Claim 6

The photo mask pattern designing method according to claim 1 wherein said pattern configuration of said single-layered resist pattern is divided into pattern configurations having substantially the same line width and substantially the same pitch.

Claim 7

The photo mask pattern designing method of claim 1 , wherein said first photo mask and said second photo mask are used to fabricate a Single-layered resist pattern on a resist coated on a substrate.

Claim 8

The photo mask pattern designing method of claim 1 , wherein: exposure of said corrected first shading region has corrected first optimum exposure values; exposure of said corrected second shading region has corrected second optimum exposure values; said corrected first optimum exposure values being substantially equal to said corrected second optimum exposure values.

Claim 9

The photo mask pattern designing method of claim 7 , wherein: said corrected first optimum exposure values including a first range of exposure values and a first range of focus values; said corrected second optimum exposure values including a second range of exposure values and a second range of focus values; said first range of exposure values overlapping said second range of exposure values; said first range of focus values overlapping said second range of focus values.

Claim 10

The photo mask pattern designing method of claim 7 , wherein: said second shading region is corrected in width prior to correcting said first shading region in width, said first shading region being corrected in width only when correction in width of said second shading region fails to bring about said corrected first optimum exposure values as substantially equal to said corrected second optimum exposure values.

Claim 11

A resist pattern fabricating method configured to fabricate a single-layered resist pattern on a resist coated on a substrate by executing a plurality of times of exposure including first exposure using a first photo mask and interference of light and a second exposure using a second photo mask, characterized in that: a first shading region formed on said first photo mask and a second shading region formed on said second photo mask are substantially aligned in location on said first photo mask and said second photo mask; and a first translucent region formed on said first photo mask and a second translucent region formed on said second photo mask are substantially aligned in location on said first photo mask and said second photo mask, and comprising the steps of: conducting said first exposure of said first shading region by using said first photo mask corrected in width in the direction of adjacent alignment of said first shading region and said first translucent region; and conducting said second exposure of said second shading region by using said second photo mask corrected in width in the direction of adjacent alignment of said second shading region and said second translucent region.

Claim 12

A resist pattern fabricating method configured to fabricate a single-layered resist pattern on a resist coated on a substrate by executing a plurality of times of exposure including first exposure using a first photo mask and interference of light and a second exposure using a second photo mask, characterized in that: a first shading region formed on said first photo mask and a second shading region formed on said second photo mask are substantially aligned in location on said first photo mask and said second photo mask; and a first translucent region formed on said first photo mask and a second translucent region formed on said second photo mask are substantially aligned in location on said first photo mask and said second photo mask, and comprising the steps of: conducting said first exposure of said first shading region by using said first photo mask corrected in width in the direction of adjacent alignment of said first shading region and said first translucent region; and conducting said second exposure of said second shading region by using said second photo mask corrected in width in the direction of adjacent alignment of said second shading region and said second translucent region.

Claim 13

The resist pattern fabricating method according to claim 10 wherein correction of said second shading region in said second photo mask is preferentially conducted.

Claim 14

The resist pattern fabricating method according to claim 10 wherein said first photo mask is a phase shift mask.

Claim 15

The resist pattern fabricating method according to claim 10 wherein said second photo mask is a binary mask.

Claim 16

The resist pattern fabricating method as set forth in claim 10 , wherein said first photo mask and said second photo mask are patterned.

Claim 17

The resist pattern fabricating method as set forth in claim 10 , wherein exposure of said corrected first shading region has corrected first optimum exposure values; exposure of said corrected second shading region has corrected second optimum exposure values; said corrected first optimum exposure values being substantially equal to said corrected second optimum exposure values.

Claim 18

The photo mask pattern designing method of claim 15 , wherein: said corrected first optimum exposure values including a first range of exposure values and a first range of focus values; said corrected second optimum exposure values including a second range of exposure values and a second range of focus values; said first range of exposure values overlapping said second range of exposure values; said first range of focus values overlapping said second range of focus values.

Claim 19

The photo mask pattern designing method of claim 15 , wherein: said second shading region is corrected in width prior to correcting said first shading region in width, said first shading region being corrected in width only when correction in width of said second shading region fails to bring about said corrected first optimum exposure values as substantially equal to said corrected second optimum exposure values.

Claim 20

A semiconductor device manufacturing method configured to make a resist pattern on a resist coated on a semiconductor substrate by executing a plurality of times of exposure including first exposure using a first photo mask and interference of light and second exposure using a second photo mask, and thereafter process said semiconductor substrate by using said resist pattern as a mask, characterized in that: a first shading region formed on said first photo mask and a second shading region formed on said second photo mask are substantially aligned in location on said first photo mask and said second photo mask; and a first translucent region formed on said first photo mask and a second translucent region formed on said second photo mask are substantially aligned in location on said first photo mask and said photo mask, and comprising the steps of: conducting said first exposure of said first shading region by using said first photo mask corrected in width in the direction of adjacent alignment of said first shading region and said first translucent region; and conducting said second exposure of said second shading region by using said second photo mask corrected in width in the direction of adjacent alignment of said second shading region and said second translucent region.

Claim 21

A semiconductor device manufacturing method configured to make a resist pattern on a resist coated on a semiconductor substrate by executing a plurality of times of exposure including first exposure using a first photo mask and interference of light and second exposure using a second photo mask, and thereafter process said semiconductor substrate by using said resist pattern as a mask, characterized in that: a first shading region formed on said first photo mask and a second shading region formed on said second photo mask are substantially aligned in location on said first photo mask and said second photo mask; and a first translucent region formed on said first photo mask and a second translucent region formed on said second photo mask are substantially aligned in location on said first photo mask and said photo mask, and comprising the steps of: conducting said first exposure of said first shading region by using said first photo mask corrected in width in the direction of adjacent alignment of said first shading region and said first translucent region; and conducting said second exposure of said second shading region by using said second photo mask corrected in width in the direction of adjacent alignment of said second shading region and said second translucent region.

Claim 22

The semiconductor device manufacturing method according to claim 18 wherein correction of said second shading region in said second photo mask is preferentially conducted.

Claim 23

The semiconductor device manufacturing method according to claim 18 wherein said first photo mask is a phase shift mask.

Claim 24

The semiconductor device manufacturing method according to claim 18 wherein said second photo mask is a binary mask.

Claim 25

The semiconductor device manufacturing method as set forth in claim 18 , wherein said first photo mask and said second photo mask are patterned.

Claim 26

The semiconductor device manufacturing method as set forth in claim 18 , wherein: exposure of said corrected first shading region has corrected first optimum exposure values; exposure of said corrected second shading region has corrected second optimum exposure values; said corrected first optimum exposure values being substantially equal to said corrected second optimum exposure values.

Claim 27

The photo mask pattern designing method of claim 23 , wherein: said corrected first optimum exposure values including a first range of exposure values and a first range of focus values; said corrected second optimum exposure values including a second range of exposure values and a second range of focus values; said first range of exposure values overlapping said second range of exposure values; said first range of focus values overlapping said second range of focus values.

Claim 28

The photo mask pattern designing method of claim 23 , wherein: said second shading region is corrected in width prior to correcting said first shading region in width, said first shading region being corrected in width only when correction in width of said second shading region fails to bring about said corrected first optimum exposure values as substantially equal to said corrected second optimum exposure values.