Design methodology for inserting RAM clock delays

Claim 1

A method of designing a semiconductor integrated circuit including at least one data-processing unit and at least one random-access memory macrocell, the random-access memory macrocell having a set-up timing requirement, the method using computer-aided design tools and a hardware description language and comprising the steps of: automatically generating a clock tree, by use of the computer-aided design tools, the clock tree including a first clock path having a root cell at which a clock signal is generated, a leaf cell disposed in the random-access memory macrocell, and at least one buffer disposed between the root cell and the leaf cell, and a second clock path beginning at said root cell and terminating in the at least one data-processing unit; and modifying the clock tree, by use of the computer-aided design tools, thereby increasing a clock propagation delay on said first clock path relative to said second clock path, so as to satisfy the set-up timing requirement.

Claim 2

A method of designing a semiconductor integrated circuit including at least one data-processing unit and at least one random-access memory macrocell, the random-access memory macrocell having a set-up timing requirement, the method using computer-aided design tools and a hardware description language and comprising the steps of: automatically generating a clock tree, by use of the computer-aided design tools, the clock tree including a first clock path having a root cell at which a clock signal is generated, a leaf cell disposed in the random-access memory macrocell, and at least one buffer disposed between the root cell and the leaf cell, and a second clock path beginning at said root cell and terminating in the at least one data-processing unit; and modifying the clock tree, by use of the computer-aided design tools, thereby increasing a clock propagation delay on said first clock path relative to said second clock path, so as to satisfy the set-up timing requirement.

Claim 6

A method of designing a semiconductor integrated circuit including at least one data-processing unit and at least one random-access memory macrocell, the random-access memory macrocell having a set-up timing requirement, the method using computer-aided design tools and a hardware description language and comprising the steps of: designating a root cell at which a clock signal is generated; designating a leaf cell in the random-access memory macrocell; automatically generating a first clock tree, by use of the computer-aided design tools, the first clock tree including a first clock path beginning at said root cell and terminating at said leaf cell and a second clock path beginning at said root cell and terminating in the at least one data-processing unit, the first clock path including a first buffer disposed between said leaf cell and said root cell; designating the first buffer as a leaf cell in place of the leaf cell designated in the random-access memory macrocell; and regenerating the first clock tree, by use of the computer-aided design tools, thereby obtaining a second clock tree that supplies a clock signal to the first buffer, the clock signal then being supplied to the random-access memory macrocell with a first delay by a remaining part of the first clock tree between the first buffer and the random-access memory macrocell.

Claim 7

A method of designing a semiconductor integrated circuit including at least one data-processing unit and at least one random-access memory macrocell, the random-access memory macrocell having a set-up timing requirement, the method using computer-aided design tools and a hardware description language and comprising the steps of: designating a root cell at which a clock signal is generated; designating a leaf cell in the random-access memory macrocell; automatically generating a first clock tree, by use of the computer-aided design tools, the first clock tree including a first clock path beginning at said root cell and terminating at said leaf cell and a second clock path beginning at said root cell and terminating in the at least one data-processing unit, the first clock path including a first buffer disposed between said leaf cell and said root cell; designating the first buffer as a leaf cell in place of the leaf cell designated in the random-access memory macrocell; and regenerating the first clock tree, by use of the computer-aided design tools, thereby obtaining a second clock tree that supplies a clock signal to the first buffer, the clock signal then being supplied to the random-access memory macrocell with a first delay by a remaining part of the first clock tree between the first buffer and the random-access memory macrocell.

Claim 11

A method of designing a semiconductor integrated circuit including at least one random-access memory macrocell, using computer-aided design tools and a hardware description language, comprising the steps of: designating a root cell at which a clock signal is generated; designating a leaf cell in the random-access memory macrocell; automatically generating a first clock tree, by use of the computer-aided design tools, the first clock tree including a clock path beginning at said root cell and terminating at said leaf cell, the clock path including a first buffer disposed between said leaf cell and said root cell; and down-sizing the first buffer by decreasing transistor dimensions in the first buffer, thereby reducing a current-driving capability of the first buffer and obtaining a second clock tree that supplies a clock signal to the random-access memory macrocell with a first delay; checking for design constraint violations after said step of down-sizing; performing a timing analysis to determine whether the second clock tree provides an adequate set-up timing margin for the random-access memory macrocell, provided no design constraints are violated in said step of checking; further down-sizing the first buffer if the set-up timing margin is inadequate; and if a design constraint is violated in said step of checking, and if the second clock tree has a second buffer disposed between the leaf cell and the root cell, down-sizing the second buffer by decreasing transistor dimensions in the second buffer, instead of down-sizing the first buffer.

Claim 12

A method of designing a semiconductor integrated circuit including at least one random-access memory macrocell, using computer-aided design tools and a hardware description language, comprising the steps of: designating a root cell at which a clock signal is generated; designating a leaf cell in the random-access memory macrocell; automatically generating a first clock tree, by use of the computer-aided design tools, the first clock tree including a clock path beginning at said root cell and terminating at said leaf cell, the clock path including a first buffer disposed between said leaf cell and said root cell; and down-sizing the first buffer by decreasing transistor dimensions in the first buffer, thereby reducing a current-driving capability of the first buffer and obtaining a second clock tree that supplies a clock signal to the random-access memory macrocell with a first delay; checking for design constraint violations after said step of down-sizing; performing a timing analysis to determine whether the second clock tree provides an adequate set-up timing margin for the random-access memory macrocell, provided no design constraints are violated in said step of checking; further down-sizing the first buffer if the set-up timing margin is inadequate; and if a design constraint is violated in said step of checking, and if the second clock tree has a second buffer disposed between the leaf cell and the root cell, down-sizing the second buffer by decreasing transistor dimensions in the second buffer, instead of down-sizing the first buffer.

Claim 14

A method of designing a semiconductor integrated circuit including at least one random-access memory macrocell, using computer-aided design tools and a hardware description language, comprising the steps of: designating a root cell at which a clock signal is generated; designating a leaf cell in the random-access memory macrocell; automatically generating a first clock tree, by use of the computer-aided design tools, the first clock tree including a clock path beginning at said root cell and terminating at said leaf cell, the clock path including a first buffer disposed between said leaf cell and said root cell; and down-sizing the first buffer by decreasing transistor dimensions in the first buffer, thereby reducing a current-driving capability of the first buffer and obtaining a second clock tree that supplies a clock signal to the random-access memory macrocell with a first delay; checking for design constraint violations after said step of down-sizing; repeating said step of down-sizing until a design constraint violation is found in said step of checking; disregarding the repetition of said step of down-sizing that caused the design constraint violation; performing a timing analysis to determine whether the second clock tree provides an adequate set-up timing margin for the random-access memory macrocell, after said step of disregarding; and if the set-up timing margin is inadequate, and if the second clock tree has a second buffer disposed between the leaf cell and the root cell, down-sizing the second buffer by decreasing transistor dimensions in the second buffer, thereby obtaining a third clock tree that supplies a clock signal to the random-access memory macrocell with a second delay greater than the first delay.

Claim 15

A method of designing a semiconductor integrated circuit including at least one random-access memory macrocell, using computer-aided design tools and a hardware description language, comprising the steps of: designating a root cell at which a clock signal is generated; designating a leaf cell in the random-access memory macrocell; automatically generating a first clock tree, by use of the computer-aided design tools, the first clock tree including a clock path beginning at said root cell and terminating at said leaf cell, the clock path including a first buffer disposed between said leaf cell and said root cell; and down-sizing the first buffer by decreasing transistor dimensions in the first buffer, thereby reducing a current-driving capability of the first buffer and obtaining a second clock tree that supplies a clock signal to the random-access memory macrocell with a first delay; checking for design constraint violations after said step of down-sizing; repeating said step of down-sizing until a design constraint violation is found in said step of checking; disregarding the repetition of said step of down-sizing that caused the design constraint violation; performing a timing analysis to determine whether the second clock tree provides an adequate set-up timing margin for the random-access memory macrocell, after said step of disregarding; and if the set-up timing margin is inadequate, and if the second clock tree has a second buffer disposed between the leaf cell and the root cell, down-sizing the second buffer by decreasing transistor dimensions in the second buffer, thereby obtaining a third clock tree that supplies a clock signal to the random-access memory macrocell with a second delay greater than the first delay.