Semiconductor device carrying memory and logic circuit on a chip and method of manufacturing the same

Claim 2

A semiconductor device comprising: a semiconductor substrate; a logic region formed in said semiconductor substrate and including an element forming layer; a memory region formed in said semiconductor substrate and including an element forming layer; a multilayer wiring layer formed above each of said logic region and said memory region; and a diffusion preventing film formed at least between said multilayer wiring layer in said logic region and said element forming layer in said logic region, said diffusion preventing film being adapted to prevent H 2 O from diffusing into said logic region.

Claim 3

The device according to claim 1 , said multilayer wiring layer comprising: an interlayer insulating film having a dielectric constant lower than that of silicon oxide film; and wires arranged in said interlayer insulating film.

Claim 4

The device according to claim 1 , wherein said diffusion preventing film is arranged at least between the gate insulating films of the transistors formed in said logic region and said low dielectric constant interlayer insulating film arranged above them.

Claim 5

The device according to claim 1 , wherein said diffusion preventing film is a silicon oxide film containing nitrogen.

Claim 6

The device according to claim 4 , wherein the nitrogen content of said silicon oxide film is 8.8 to 9.8 atomic %.

Claim 7

The device according to claim 4 , wherein the nitrogen content of said silicon oxide film is 5 to 15 atomic %.

Claim 8

A semiconductor device comprising: a semiconductor substrate; a logic region formed in said semiconductor substrate and including an element forming layer; a memory region formed in said semiconductor substrate and including an element forming layer; a multilayer wiring layer formed above said logic region and said memory region; a diffusion preventing film formed between said element forming layers of said logic region and said memory region and said multilayer wiring layer, said diffusion preventing film being adapted to prevent H 2 O from diffusion; and openings formed in said diffusion preventing film of said memory region.

Claim 9

A semiconductor device comprising: a semiconductor substrate; a logic region formed in said semiconductor substrate and including an element forming layer; a memory region formed in said semiconductor substrate and including an element forming layer; a multilayer wiring layer formed above said logic region and said memory region; a diffusion preventing film formed between said element forming layers of said logic region and said memory region and said multilayer wiring layer, said diffusion preventing film being adapted to prevent H 2 O from diffusion; and openings formed in said diffusion preventing film of said memory region.

Claim 10

The device according to claim 7 , wherein said openings are formed among a plurality of wiring layers arranged in one of the layers of said multilayer wiring layer and each of said openings is arranged for a plurality of memory cells formed in said memory region.

Claim 11

The device according to claim 7 , wherein each of said openings are formed between two adjacent wiring layers arranged in one of the layers of said multilayer wiring layer and arranged for a plurality of wires.

Claim 12

The device according to claim 7 , said multilayer wiring layer comprising: an interlayer insulating film having a dielectric constant lower than that of silicon oxide film; and wires arranged in said interlayer insulating film.

Claim 13

The device according to claim 7 , wherein said diffusion preventing film is a silicon oxide film containing nitrogen.

Claim 14

The device according to claim 10 , wherein the nitrogen content of said silicon oxide film is 8.8 to 9.8 atomic %.

Claim 15

The device according to claim 10 , wherein the nitrogen content of said silicon oxide film is 5 to 15 atomic %.

Claim 16

A semiconductor device comprising: a semiconductor substrate; a logic region formed in said semiconductor substrate and including an element forming layer; a memory region formed in said semiconductor substrate and including an element forming layer; a multilayer wiring layer formed above said logic region and said memory region; a first diffusion preventing film formed between said logic region and said multilayer wiring layer, said first diffusion preventing film being adapted to prevent H 2 O from diffusion; and an insulating film formed between said memory region and said multilayer wiring layer and adapted to operate as H 2 supply source.

Claim 17

A semiconductor device comprising: a semiconductor substrate; a logic region formed in said semiconductor substrate and including an element forming layer; a memory region formed in said semiconductor substrate and including an element forming layer; a multilayer wiring layer formed above said logic region and said memory region; a first diffusion preventing film formed between said logic region and said multilayer wiring layer, said first diffusion preventing film being adapted to prevent H 2 O from diffusion; and an insulating film formed between said memory region and said multilayer wiring layer and adapted to operate as H 2 supply source.

Claim 18

The device according to claim 14 , further comprising: a second diffusion preventing film formed between said insulating film and said multilayer wiring layer.

Claim 19

The device according to claim 14 , said multilayer wiring layer comprising: an interlayer insulating film having a dielectric constant lower than that of silicon oxide film; and wires arranged in said interlayer insulating film.

Claim 20

The device according to claim 14 , wherein said first and second diffusion preventing film are silicon oxide films containing nitrogen.

Claim 21

The device according to claim 17 , wherein the nitrogen content of said silicon oxide film is 8.8 to 9.8 atomic %.

Claim 22

The device according to claim 17 , wherein the nitrogen content of said silicon oxide film is 5to 15 atomic %.