US6570570B1
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Parallel processing processor and parallel processing method
Assignee: Renesas Electronics Corp
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Filing: 1999-07-19
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Granted: 2003-05-27
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Expires: 2019-07-19
Abstract
Abstract A parallel processing processor for processing images including alpha data indicative of pixel transparency. The parallel processing processor comprises: a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction; general purpose registers which are connected to the execution units via a data path, which input data to the execution units and which receive results of operations from the execution units; alpha data dedicated registers which are connected to the execution units via another data path and which input data to the execution units; and a control circuit for directing data from the general purpose registers and alpha data dedicated registers into each of the execution units under control of a single instruction. Under the instruction, the execution units admit data from the general purpose registers to carry out first arithmetic and logical operation in parallel on the admitted data and, without returning result of the first arithmetic and logical operation to the general purpose registers, receive data from the alpha data dedicated registers to perform second arithmetic and logical operation in parallel between the received data and the result of first arithmetic and logical operation.
Inventors
- 👤 Yoshinori Suzuki
- 👤 Junichi Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F9/3887; G06T; G06T15/00; G06T15/005; G09; G09G; G09G2340/00; G09G2340/10; G09G2352/00
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
126 words
A parallel processing processor for processing images including α data indicative of pixel transparency, said parallel processing processor comprising: (a) a plurality of execution units for parallelly executing arithmetic and logical operations under control of a single instruction; (b) a general purpose register which is connected to said execution units via a data path, which inputs data to said execution units and which receives results of operations from said execution units; (c) an α data dedicated register which is connected to said execution units via another data path and which inputs data to said execution units; and (d) controlling means for directing data from said general purpose register and said α data dedicated register into each of said execution units under control of a single instruction.
Claim 2
Dependent Claim
126 words
A parallel processing processor for processing images including α data indicative of pixel transparency, said parallel processing processor comprising: (a) a plurality of execution units for parallelly executing arithmetic and logical operations under control of a single instruction; (b) a general purpose register which is connected to said execution units via a data path, which inputs data to said execution units and which receives results of operations from said execution units; (c) an α data dedicated register which is connected to said execution units via another data path and which inputs data to said execution units; and (d) controlling means for directing data from said general purpose register and said α data dedicated register into each of said execution units under control of a single instruction.
Claim 3
Dependent Claim
172 words
A parallel processing processor for processing images including α data indicative of pixel transparency, said parallel processing processor comprising: (a) a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction; (b) a general purpose register which is connected to said execution units via a data path, which inputs data to said execution units and which receives results of operations from said execution units; and (c) an α data dedicated register which is connected to said execution units via another data path and which inputs data to said execution units; wherein, under control of a single instruction, said execution units admit data from said general purpose register to carry out first arithmetic and logical operation on the admitted data and, without returning result of said first arithmetic and logical operation to said general purpose register, receive data from said α data dedicated register to perform second arithmetic and logical operation between the received data and the result of said first arithmetic and logical operation.
Claim 4
Dependent Claim
172 words
A parallel processing processor for processing images including α data indicative of pixel transparency, said parallel processing processor comprising: (a) a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction; (b) a general purpose register which is connected to said execution units via a data path, which inputs data to said execution units and which receives results of operations from said execution units; and (c) an α data dedicated register which is connected to said execution units via another data path and which inputs data to said execution units; wherein, under control of a single instruction, said execution units admit data from said general purpose register to carry out first arithmetic and logical operation on the admitted data and, without returning result of said first arithmetic and logical operation to said general purpose register, receive data from said α data dedicated register to perform second arithmetic and logical operation between the received data and the result of said first arithmetic and logical operation.
Claim 5
Dependent Claim
37 words
A parallel processing processor according to claim 1 , wherein the data in said general purpose register is a result of operations on color data and the data in said α data dedicated register is α data.
Claim 6
Dependent Claim
57 words
A parallel processing processor according to claim 1 , further comprising an α data transform circuit for transforming α data into mask data made of either 0's or 1's, wherein, under control of a single instruction, said α data transform circuit performs the data transformation and said mask data are loaded into said α data dedicated register.
Claim 7
Dependent Claim
57 words
A parallel processing processor according to claim 1 , further comprising an α data transform circuit for transforming α data into mask data made of either 0's or 1's, wherein, under control of a single instruction, said α data transform circuit performs the data transformation and said mask data are loaded into said α data dedicated register.
Claim 8
Dependent Claim
80 words
A parallel processing processor according to claim 1 , further comprising an α data transform circuit for comparing input α data with a predetermined threshold value and for transforming said α data into binary data all made up of either 0 bits or 1 bits depending on an outcome of the comparison, wherein, under control of a single instruction, said α data transform circuit performs the data transformation and said binary data are loaded into said α data dedicated register.
Claim 9
Dependent Claim
78 words
A parallel processing processor according to claim 1 , further comprising an α data transform circuit for comparing input α data with a predetermined threshold value and for transforming said α data into mask data all made up of either 0's or 1's depending on an outcome of the comparison, wherein, under control of a single instruction, said α data transform circuit performs the data transformation and said mask data are loaded into said α data dedicated register.
Claim 10
Dependent Claim
64 words
A parallel processing processor according to claim 2 , wherein said α data dedicated register is constituted by a plurality of addressable registers, and wherein said execution units admit data from one of the addressable registers which is designated by an instruction and perform said second arithmetic and logical operation between the admitted data and the result of said first arithmetic and logical operation.
Claim 11
Dependent Claim
89 words
A parallel processing processor according to claim 2 , wherein said α data dedicated register is constituted by a plurality of registers, each address of which corresponds to that of register inside said general purpose register, and wherein said execution units admit data from one of said α data dedicated registers corresponding in addressing to one of said general purpose registers which is designated by an instruction and perform said second arithmetic and logical operation between the admitted data and the result of said first arithmetic and logical operation.
Claim 12
Dependent Claim
42 words
A parallel processing processor according to claim 5 , wherein the mask data output by said α data transform circuit and input to said a data dedicated register as well as to said execution units is one bit data for each pixel.
Claim 13
Dependent Claim
154 words
A parallel processing method for use with a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction, said parallel processing method processing images including α data indicative of pixel transparency and comprising the steps of: (a) inputting a plurality of first data from a general purpose register to said execution units for performing first arithmetic and logical operation in parallel by the units; (b) inputting a plurality of second data corresponding to said first data from an α data dedicated register to said execution units without returning result of said first arithmetic and logical operation to said general purpose register, so as to perform second arithmetic and logical operation in parallel between said second data and said result of said first arithmetic and logical operation; and (c) outputting result of said second arithmetic and logical operation to a general purpose register designated by an instruction.
Claim 14
Dependent Claim
154 words
A parallel processing method for use with a plurality of execution units for executing in parallel arithmetic and logical operations under control of a single instruction, said parallel processing method processing images including α data indicative of pixel transparency and comprising the steps of: (a) inputting a plurality of first data from a general purpose register to said execution units for performing first arithmetic and logical operation in parallel by the units; (b) inputting a plurality of second data corresponding to said first data from an α data dedicated register to said execution units without returning result of said first arithmetic and logical operation to said general purpose register, so as to perform second arithmetic and logical operation in parallel between said second data and said result of said first arithmetic and logical operation; and (c) outputting result of said second arithmetic and logical operation to a general purpose register designated by an instruction.
Claim 15
Dependent Claim
39 words
A parallel processing method according to claim 11 , wherein said first data in said general purpose register is a result of operations on color data and said second data in said α data dedicated register is α data.
Claim 16
Dependent Claim
51 words
A parallel processing method according to claim 11 , further comprising the step of transforming α data into binary data all made up of either 0 bits or 1 bits under control of another single instruction, said binary data being loaded as said second data into said α data dedicated register.
Claim 17
Dependent Claim
48 words
A parallel processing method according to claim 11 , further comprising the step of transforming α data into mask data of either value 0 or value 1 under control of another single instruction, said mask data being loaded as said second data into said α data dedicated register.
Claim 18
Dependent Claim
69 words
A parallel processing method according to claim 11 , further comprising the step of, under control of another single instruction, comparing input α data with a predetermined threshold value and transforming said α data into binary data all made up of either 0 bits or 1 bits depending on an outcome of the comparison, said binary data being loaded as said second data into said a data dedicated register.
Claim 19
Dependent Claim
66 words
A parallel processing method according to claim 11 , further comprising the step of, under control of another single instruction, comparing input α data with a predetermined threshold value and transforming said α data into mask data of either value 0 or value 1 depending on an outcome of the comparison, said mask data being loaded as said second data into said a data dedicated register.
Claim 20
Dependent Claim
72 words
A parallel processing method according to claim 11 , wherein said α data dedicated register is constituted by a plurality of addressable registers, said parallel processing method further comprising the step of causing said execution units to admit data from one of the addressable registers which is designated by six instruction and to perform said second arithmetic and logical operation between the admitted data and the result of said first arithmetic operation.
Claim 21
Dependent Claim
98 words
A parallel processing method according to claim 11 , wherein said α data dedicated register is constituted by a plurality of registers, each address of which corresponds to that of register inside said general purpose register, said parallel processing method further comprising the step of causing said execution units to admit data from one of said α data dedicated registers corresponding in addressing to one of said general purpose registers which is designated by an instruction and perform said second arithmetic and logical operation between the admitted data and the result of said first arithmetic and logical operation.
Claim 22
Dependent Claim
45 words
A parallel processing method according to claim 14 , further comprising the step of transforming said α data into one bit mask data of either value 0 or value 1 and loading said mask data as said second data into said α data dedicated register.
Claim 23
Dependent Claim
98 words
A parallel processing method according to claim 11 , wherein said α data dedicated register is constituted by a plurality of registers, each address of which corresponds to that of register inside said general purpose register, said parallel processing method further comprising the step of causing said execution units to admit data from one of said α data dedicated registers corresponding in addressing to one of said general purpose registers which is designated by an instruction and perform said second arithmetic and logical operation between the admitted data and the result of said first arithmetic and logical operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-05-26 | 2006-11-25 | 2007-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-26 | 2010-11-25 | 2011-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-26 | 2014-11-25 | 2015-05-27 | $7700.00 | Window Closed / Lapsed |