US6557108B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method in a modem for providing a shortened reset pulse upon receipt of an external reset pulse
Assignee: HP Inc
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Filing: 1999-05-28
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Granted: 2003-04-29
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Expires: 2019-05-28
Abstract
Abstract A system and method for providing a shortened DSP reset pulse to cause a modem to reset and enter a sleep mode as soon as possible after receipt of an external reset pulse issued by a host. A reset controller detects the external reset pulse, issues a separate reset pulse to the modem, monitors the modem's clock and then terminates the separate reset pulse after a prescribed duration. The prescribed duration is determined by the minimum time required by the DSP to reset. The invention is embodied in a modem connected to an external controller. The modem includes a DSP having a reset terminal and a clock. The DSP begins performing a reset upon a first signal applied to its reset terminal and causes the modem to enter a sleep-mode after a second signal is applied to its reset terminal. The external controller is capable of transmitting an external signal. The reset controller in the modem has a counter and an output node. The counter is connected to the clock and provides a counter output signal upon receipt of a predetermined number of cycles of the clock. The counter initiating generally concurrent with receipt of the external signal. The output node is connected to the reset terminal of the DSP and to the output counter. The output node provides a first signal to the DSP generally concurrent with receipt of the external signal and a second signal generally concurrent with receipt of the counter output signal.
Inventors
- 👤 David Moore
- 👤 Harrison Killian
- 👤 David Arnesen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:52
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/24
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
158 words
In a modem connected to an external controller, said modem comprising a DSP having a reset terminal and an internal clock, whereby said DSP begins performing a reset upon a first signal applied to said reset terminal and causes said modem to enter a sleep-mode after a second signal is applied to said reset terminal, said external controller being capable of transmitting an external signal, a reset controller in said modem comprising: a counter connected to said DSP internal clock and providing a counter output signal upon receipt of a predetermined number of cycles of said DSP internal clock, said counter initiating generally concurrent with receipt of the external signal; and an output node connected to said reset terminal of said DSP and to said output counter, said output node providing said first signal to said DSP generally concurrent with receipt of the external signal and said second signal generally concurrent with receipt of the counter output signal.
Claim 2
Dependent Claim
158 words
In a modem connected to an external controller, said modem comprising a DSP having a reset terminal and an internal clock, whereby said DSP begins performing a reset upon a first signal applied to said reset terminal and causes said modem to enter a sleep-mode after a second signal is applied to said reset terminal, said external controller being capable of transmitting an external signal, a reset controller in said modem comprising: a counter connected to said DSP internal clock and providing a counter output signal upon receipt of a predetermined number of cycles of said DSP internal clock, said counter initiating generally concurrent with receipt of the external signal; and an output node connected to said reset terminal of said DSP and to said output counter, said output node providing said first signal to said DSP generally concurrent with receipt of the external signal and said second signal generally concurrent with receipt of the counter output signal.
Claim 3
Dependent Claim
31 words
The reset controller of claim 1 , wherein the predetermined number of cycles of said DSP internal clock is at least the minimum time said DSP requires to perform a reset.
Claim 4
Dependent Claim
37 words
The reset controller of claim 1 , wherein the predetermined number of cycles of said DSP internal clock is at least the minimum time said DSP requires to perform a reset plus a minimum margin of error.
Claim 5
Dependent Claim
20 words
The reset controller of claim 3 , wherein the reset performed by said DSP is the initialization of selected registers.
Claim 6
Dependent Claim
21 words
The reset controller of claim 4 , wherein the reset performed by,said DSP further comprises a confirmation of said reset controller.
Claim 7
Dependent Claim
23 words
The reset controller of claim 1 , wherein said counter initializes within one DSP internal clock cycle after receipt of the external signal.
Claim 8
Dependent Claim
40 words
The reset controller of claim 6 , wherein said output node is further connected to said DSP internal clock, wherein said output node provides the first signal to said DSP within one clock cycle after receipt of the external signal.
Claim 9
Dependent Claim
241 words
In a modem connected to an external bus, said external bus being controlled by a bus controller, said modem comprising an application circuit connected directly to said external bus, a DSP having a reset terminal and a DSP internal clock whereby said DSP initializes selected registers therein upon a leading edge of a reset pulse applied to said reset terminal and said DSP causes said modem to enter a sleep-mode after the trailing edge of a reset pulse applied to said reset terminal, said DSP and said application circuit connected to said DSP bus, said external bus controller being capable of transmitting on said external bus an external reset pulse of a first duration, a reset controller circuit in said modem comprising: a counter connected to said DSP internal clock and providing a counter output signal upon receipt of a predetermined number of cycles of said DSP internal clock, said counter initiating generally concurrent with receipt of the leading edge of said external reset pulse; and a pulse output node connected to said reset terminal of said DSP and to said output counter, said output node providing a leading DSP reset pulse edge generally concurrent with the leading edge of said external reset pulse and a trailing DSP pulse edge generally concurrent with said counter output signal, so as to provide a reset pulse to said DSP having a duration generally corresponding to said predetermined number of DSP internal clock cycles.
Claim 10
Dependent Claim
241 words
In a modem connected to an external bus, said external bus being controlled by a bus controller, said modem comprising an application circuit connected directly to said external bus, a DSP having a reset terminal and a DSP internal clock whereby said DSP initializes selected registers therein upon a leading edge of a reset pulse applied to said reset terminal and said DSP causes said modem to enter a sleep-mode after the trailing edge of a reset pulse applied to said reset terminal, said DSP and said application circuit connected to said DSP bus, said external bus controller being capable of transmitting on said external bus an external reset pulse of a first duration, a reset controller circuit in said modem comprising: a counter connected to said DSP internal clock and providing a counter output signal upon receipt of a predetermined number of cycles of said DSP internal clock, said counter initiating generally concurrent with receipt of the leading edge of said external reset pulse; and a pulse output node connected to said reset terminal of said DSP and to said output counter, said output node providing a leading DSP reset pulse edge generally concurrent with the leading edge of said external reset pulse and a trailing DSP pulse edge generally concurrent with said counter output signal, so as to provide a reset pulse to said DSP having a duration generally corresponding to said predetermined number of DSP internal clock cycles.
Claim 11
Dependent Claim
31 words
The reset controller of claim 8 , wherein the predetermined number of cycles of said DSP internal clock is at least the minimum time said DSP requires to initialize selected registers.
Claim 12
Dependent Claim
40 words
The reset controller of claim 8 , wherein the predetermined number of cycles of said DSP internal clock is at least the minimum time said DSP requires to confirm receipt of the DSP reset pulse and to initialize selected registers.
Claim 13
Dependent Claim
46 words
The reset controller of claim 8 , wherein the predetermined number of cycles of said DSP internal clock is at least the minimum time said DSP requires to confirm receipt of the DSP reset pulse and to initialize selected registers plus a predetermined margin of error.
Claim 14
Dependent Claim
24 words
The reset controller of claim 11 , wherein said counter initializes within one DSP internal clock cycle of receipt of the external reset pulse.
Claim 15
Dependent Claim
46 words
The reset controller of claim 12 , wherein said pulse output node is further connected to said DSP internal clock, wherein said pulse output node provides the leading DSP reset pulse edge to said DSP within one DSP internal clock cycle of the external reset pulse.
Claim 16
Dependent Claim
50 words
The reset controller of claim 13 , wherein said pulse output node comprises a flip-flop circuit having a first input of the output counter signal, a second input of the external reset pulse, a clock input of the DSP internal clock signal and an output to said DSP reset terminal.
Claim 17
Dependent Claim
131 words
In a modem providing a modulator/demodulator function connected between an external bus controlled by an external controller and an analog port, said modem comprising a DSP having a reset terminal and a DSP internal clock, whereby said DSP begins performing a reset upon a signal applied to said reset terminal and causes said modem to enter a sleep-mode after the signal is terminated, said external controller being capable of transmitting an external signal, a method for providing a shortened reset signal to said DSP reset terminal, comprising the steps of: asserting a reset signal to said DSP reset terminal generally concurrently with receipt of the external reset signal, and deasserting the reset signal upon completion of a predetermined number of clock cycles of said DSP internal clock, after said asserting step.
Claim 18
Dependent Claim
131 words
In a modem providing a modulator/demodulator function connected between an external bus controlled by an external controller and an analog port, said modem comprising a DSP having a reset terminal and a DSP internal clock, whereby said DSP begins performing a reset upon a signal applied to said reset terminal and causes said modem to enter a sleep-mode after the signal is terminated, said external controller being capable of transmitting an external signal, a method for providing a shortened reset signal to said DSP reset terminal, comprising the steps of: asserting a reset signal to said DSP reset terminal generally concurrently with receipt of the external reset signal, and deasserting the reset signal upon completion of a predetermined number of clock cycles of said DSP internal clock, after said asserting step.
Claim 19
Dependent Claim
29 words
The method of claim 15 , wherein asserting the reset to said DSP reset terminal occurs within one DSP internal clock cycle of receipt of the external reset signal.
Claim 20
Dependent Claim
26 words
The method of claim 15 , wherein the predetermined number of clock cycles is at least the minimum time said DSP requires to perform a reset.
Claim 21
Dependent Claim
32 words
The method of claim 15 , wherein the predetermined number of clock cycles is at least the minimum time said DSP requires to perform a reset plus a predetermined margin of error.
Claim 22
Dependent Claim
17 words
The method of claim 18 , wherein the reset performed by said DSP is initializing selected registers.
Claim 23
Dependent Claim
19 words
The method of claim 19 , wherein the reset performed by said DSP further comprises confirming the reset signal.
Claim 24
Dependent Claim
27 words
The method of claim 15 , wherein the asserting of the reset signal to said DSP reset terminal comprises issuing a leading edge of a pulse waveform.
Claim 25
Dependent Claim
22 words
The method of claim 21 , wherein the deasserting of the reset signal comprising issuing a trailing edge of the pulse waveform.
Claim 26
Dependent Claim
15 words
The method of claim 22 , wherein said pulse waveform is a negative asserted pulse.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-04-28 | 2006-10-28 | 2007-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-28 | 2010-10-28 | 2011-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-28 | 2014-10-28 | 2015-04-29 | $7700.00 | Window Closed / Lapsed |