US6556158B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Residue-compensating A/D converter
Assignee: Analog Devices BV
•
Filing: 2001-03-05
•
Granted: 2003-04-29
•
Expires: 2021-03-05
Abstract
Abstract An analog-to-digital converter system [ 50 D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [ 154 ] generates a first digital signal, d 0 (k), representing the sum of the input signal, g, and a dithering signal, y 0. A digital-to-analog converter [ 156 ] generates an analog feedback signal, alpha, representing accurately the first digital signal, d 0 (k). The DAC [ 156 ] may be linearized by the use of mismatch-shaping techniques. A filter [ 158 ] generates the dithering signal, y 0, by selectively amplifying in the signal band the residue signal, r 0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [ 166][168 ] are used to minimize the closed-loop signal transfer function from g to y 0, which ideally will be zero. An analog compensation signal, m 0, which is described by a well-controlled relationship to the residue signal, r 0, is extracted from the filter [ 158 ]. Ideally, the closed-loop signal transfer function from g to m 0 will be zero, or at least small in the signal band. A second quantizer [ 160 ] converts the analog compensation signal, m 0, into a second digital signal, dm 0 (k). The two digital signals, d 0 (k) and dm 0 (k), are filtered individually and then added to form the overall output signal, d g (k). The second digital filter [ 164 ] has a low signal-band gain, which implies that the sensitivity to signal-band errors caused by the second quantizer [ 160 ] will be low. The output signal, d g (k), is a highly-accurate high-resolution representation of the input signal, g. Circuit imperfections, such as mismatch, gain errors, and nonlinearities, will cause only noise-like errors having a very low spectral power density in the signal band. The invention facilitates the implementation of uncalibrated highly-linear high-resolution wide-bandwidth A/D converters [ 50 D], e.g., for use in digital communication systems, such as xDSL modems and other demanding consumer-market products for which low cost is of the essence.
Inventors
- 👤 Jesper Steensgaard-Madsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:37
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/39; H03M3/412; H03M3/414; H03M3/416; H03M1/00; H03M1/12; H03M1/14; H03M1/145
Claims Analysis
Total Claims: 50
Claim 1
Independent Claim
170 words
A method for converting an analog input signal to a digital output signal comprising the steps of: (a) generating a first digital signal comprising a signal component representing a combination of said analog input signal and a dithering signal; (b) generating an analog feedback signal by digital-to-analog converting said first digital signal; (c) generating an analog residue signal by combining said analog input signal and said analog feedback signal; (d) generating an analog compensation signal using a method comprising the step of processing said residue signal with a first analog filter of at least zeroth order; (e) generating said dithering signal using a method comprising the step of processing said analog residue signal with a second analog filter; the order said second analog filter is at least one higher than the order of said first analog filter; (f) generating a second digital signal comprising a signal component representing said analog compensation signal; and (g) generating said digital output signal by combining said first digital signal and said second digital signal.
Claim 2
Independent Claim
170 words
A method for converting an analog input signal to a digital output signal comprising the steps of: (a) generating a first digital signal comprising a signal component representing a combination of said analog input signal and a dithering signal; (b) generating an analog feedback signal by digital-to-analog converting said first digital signal; (c) generating an analog residue signal by combining said analog input signal and said analog feedback signal; (d) generating an analog compensation signal using a method comprising the step of processing said residue signal with a first analog filter of at least zeroth order; (e) generating said dithering signal using a method comprising the step of processing said analog residue signal with a second analog filter; the order said second analog filter is at least one higher than the order of said first analog filter; (f) generating a second digital signal comprising a signal component representing said analog compensation signal; and (g) generating said digital output signal by combining said first digital signal and said second digital signal.
Claim 3
Dependent Claim
78 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said analog feedback signal comprises the steps of: (a) generating a thermometer-coded representation of said first digital signal; (b) generating a digital selector signal; (c) generating a second representation of said first digital signal by permuting said thermometer-coded representation according to said digital selector signal; (d) generating said analog feedback signal by separately digital-to-analog converting each bit in said second representation of said first digital signal.
Claim 4
Dependent Claim
48 words
The analog-to-digital conversion method of claim 2 wherein the step of generating said digital selector signal comprises the step of: (a) calculating for a segment of said digital selector signal the running sum of the first digital signal modulo the number of bits in the thermometer-coded representation thereof.
Claim 5
Dependent Claim
19 words
The analog-to-digital conversion method of claim 2 wherein the selector signal is a random or at least pseudo-random signal.
Claim 6
Dependent Claim
26 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said analog feedback signal comprises the step of: (a) providing a mismatch-shaping digital-to-analog converter.
Claim 7
Dependent Claim
28 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said dithering signal comprises the step of: (a) generating a random or at least pseudo-random signal.
Claim 8
Dependent Claim
24 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said dithering signal comprises the step of: (a) providing a switched-capacitor filter.
Claim 9
Dependent Claim
20 words
The analog-to-digital conversion method of claim 1 wherein said first analog filter provides amplification which is essentially independent of frequency.
Claim 10
Dependent Claim
25 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said second digital signal comprises the step of providing a pipeline analog-to-digital converter.
Claim 11
Dependent Claim
28 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said second digital signal comprises the step of providing an analog-to-digital converter comprising a negative-feedback loop.
Claim 12
Dependent Claim
16 words
The analog-to-digital conversion method of claim 1 wherein said analog residue signal is a continuous-time signal.
Claim 13
Dependent Claim
19 words
The analog-to-digital conversion method of claim 1 wherein said first analog filter is embodied in said second analog filter.
Claim 14
Dependent Claim
17 words
The analog-to-digital conversion method of claim 1 wherein said first analog filter is a first-order integrating circuit.
Claim 15
Dependent Claim
27 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said analog residue signal comprises the step of: (a) combining at least two charge-transfer signals.
Claim 16
Dependent Claim
66 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said digital output signal comprises the steps of: (a) generating a digital residue signal by processing said second digital signal with a digital filter; (b) adjusting said digital filter's transfer function such that said digital residue signal is a digital representation of a difference between said analog input signal and said first digital signal.
Claim 17
Dependent Claim
19 words
The analog-to-digital conversion method of claim 1 wherein the order of said first analog filter is at most two.
Claim 18
Dependent Claim
47 words
The analog-to-digital conversion method of claim 1 wherein said second analog filter emphasizes in a selected frequency band the spectral components of said analog residue signal; said selected frequency band being characterized by a particularly good equivalence of said analog input signal and said digital output signal.
Claim 19
Dependent Claim
20 words
The analog-to-digital conversion method of claim 1 wherein said analog compensation signal is essentially uncorrelated to said analog input signal.
Claim 20
Dependent Claim
35 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said analog compensation signal comprises the step of: (a) combining the analog feedback signal and the signal provided by the first analog filter.
Claim 21
Dependent Claim
35 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said analog compensation signal comprises the step of: (a) combining the analog input signal and the signal provided by the first analog filter.
Claim 22
Dependent Claim
36 words
The analog-to-digital conversion method of claim 1 wherein the step of generating said digital output signal comprises the step of: (a) filtering said second digital signal with a finite-impulse-response filter having at least two non-zero coefficients.
Claim 23
Dependent Claim
26 words
The analog-to-digital conversion method of claim 1 wherein the transfer function defined from said analog input signal to said analog residue signal has a high-pass characteristic.
Claim 24
Dependent Claim
169 words
An analog-to-digital converter circuit receiving an analog input signal and providing a digital output signal comprising: (a) a first quantizer circuit generating a first digital signal representing a combination of said analog input signal and a dithering signal; (b) a digital-to-analog converter receiving said first digital signal and generating an analog feedback signal; (c) a first analog filter circuit of at least zeroth order having at least one first-named input terminal and providing an analog compensation signal; said first-named input terminal receiving a signal representing a combination of said analog input signal and said analog feedback signal; (d) a second analog filter circuit of at least first order having at least one second-named input terminal and generating said dithering signal; said second-named input terminal being connected to said first analog filter circuit; (e) a second quantizer circuit receiving said analog compensation signal and generating a digital compensation signal; (f) an output-stage digital circuit combining the first digital signal and the digital compensation signal to generate said digital output signal.
Claim 25
Dependent Claim
169 words
An analog-to-digital converter circuit receiving an analog input signal and providing a digital output signal comprising: (a) a first quantizer circuit generating a first digital signal representing a combination of said analog input signal and a dithering signal; (b) a digital-to-analog converter receiving said first digital signal and generating an analog feedback signal; (c) a first analog filter circuit of at least zeroth order having at least one first-named input terminal and providing an analog compensation signal; said first-named input terminal receiving a signal representing a combination of said analog input signal and said analog feedback signal; (d) a second analog filter circuit of at least first order having at least one second-named input terminal and generating said dithering signal; said second-named input terminal being connected to said first analog filter circuit; (e) a second quantizer circuit receiving said analog compensation signal and generating a digital compensation signal; (f) an output-stage digital circuit combining the first digital signal and the digital compensation signal to generate said digital output signal.
Claim 26
Dependent Claim
57 words
The analog-to-digital converter circuit of claim 23 wherein said first quantizer circuit comprises: (a) a flash quantizer having a first third-named input terminal of a first polarity and a second fourth-named input terminal of the opposite polarity; said third-named input terminal receiving said analog input signal; said fourth-named input terminal receiving the negative of said dithering signal.
Claim 27
Dependent Claim
52 words
The analog-to-digital converter circuit of claim 24 wherein said flash quantizer further comprises: (a) a resistor ladder conducting an essentially constant current; said resistor ladder being connected to said fourth-named input terminal and is providing a set of voltage signals which are in a predetermined relationship to said fourth-named input terminal's potential.
Claim 28
Dependent Claim
36 words
The analog-to-digital converter circuit of claim 25 wherein said resistor ladder comprises an variable impedance element, the impedance of which is controlled by a random signal; said random signal is of an at least pseudo-random nature.
Claim 29
Dependent Claim
22 words
The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter is based on a mismatch-shaping algorithm of at least zeroth order.
Claim 30
Dependent Claim
23 words
The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter is based on a idle-tone-free mismatch-shaping algorithm of at least first order.
Claim 31
Dependent Claim
33 words
The analog-to-digital converter circuit of claim 23 further comprising: (a) a circuit generating a first random signal of an at least pseudo-random nature; said random signal being partially correlated with said dithering signal.
Claim 32
Dependent Claim
35 words
The analog-to-digital converter circuit of claim 23 wherein the transfer function defined from said first-named input terminal to said analog compensation signal, when said analog feedback signal is zero, is of at most second order.
Claim 33
Dependent Claim
17 words
The analog-to-digital converter circuit of claim 23 wherein said second quantizer circuit is a pipeline analog-to-digital converter.
Claim 34
Dependent Claim
16 words
The analog-to-digital converter circuit of claim 23 wherein said second quantizer circuit comprises a noise-shaping loop.
Claim 35
Dependent Claim
17 words
The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit processes a continuous-time signal.
Claim 36
Dependent Claim
25 words
The analog-to-digital converter circuit of claim 23 wherein the transfer function from said analog input signal to said analog compensation signal has a high-pass characteristic.
Claim 37
Dependent Claim
28 words
The analog-to-digital converter circuit of claim 23 further comprising: (a) an analog front-end circuit providing said analog input signal; said analog analog front-end circuit having a high-pass characteristic.
Claim 38
Dependent Claim
13 words
The analog-to-digital converter circuit of claim 23 employed in a digital communication system.
Claim 39
Dependent Claim
19 words
The analog-to-digital converter circuit of claim 23 comprising: (a) at least one digital-to-analog converter having a smooth impulse response.
Claim 40
Dependent Claim
16 words
The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter has a deliberately-delayed impulse response.
Claim 41
Dependent Claim
22 words
The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter's effective delay is at least eighty percent of the clock period.
Claim 42
Dependent Claim
13 words
The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter is calibrated.
Claim 43
Dependent Claim
15 words
The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit is calibrated.
Claim 44
Dependent Claim
20 words
The analog-to-digital converter circuit of claim 23 wherein said dithering signal largely is virtually uncorrelated to said analog input signal.
Claim 45
Dependent Claim
32 words
The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit further comprises: (a) a third-named input terminal receiving a signal which is essentially equivalent to the analog feedback signal.
Claim 46
Dependent Claim
32 words
The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit further comprises: (a) a third-named input terminal receiving a signal which is essentially equivalent to the analog input signal.
Claim 47
Dependent Claim
15 words
The analog-to-digital converter circuit of claim 23 wherein said second analog filter circuit comprises switches.
Claim 48
Dependent Claim
17 words
The analog-to-digital converter circuit of claim 23 wherein said output-stage digital circuit delays said first digital signal.
Claim 49
Dependent Claim
21 words
The analog-to-digital converter circuit of claim 23 wherein said output-stage digital circuit filters said digital compensation signal with a finite-impulse-response filter.
Claim 50
Dependent Claim
14 words
The analog-to-digital converter circuit of claim 23 wherein said output-stage digital circuit is adaptive.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-28 | 2006-10-28 | 2007-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-28 | 2010-10-28 | 2011-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-28 | 2014-10-28 | 2015-04-29 | $7700.00 | Window Closed / Lapsed |