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US6556085B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Low power low noise amplifier

Assignee: Korea Advanced Institute of Science and Technology
•
Filing: 2001-04-09
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Granted: 2003-04-29
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Expires: 2021-04-09
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Abstract

Abstract A low power low noise amplifier achieves a high power gain without increasing power consumption by sharing the bias current. The amplifier is composed of a cascade structure which consists of a parallel connected common source transistor and common gate transistor connected to a common source transistor, an inverter type structure connected to the common source transistor, and structure improving the third-order intermodulation component using the parallel connected common source transistor and common gate transistor.

Inventors

  • 👤 Ick Jin Kwon
  • 👤 Joon Ho Gil
  • 👤 Hyung Cheol Shin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 12:20
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/193; H03F1/00; H03F1/26; H03F1/08; H03F1/22; H03F1/223; H03F2200/00; H03F2200/168; H03F2200/294; H03F2200/372

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 178 words
A low power low noise amplifier, comprising: a common source transistor M 1 ; a common source transistor M 2 ; a common gate transistor M 3 having a drain connected to a drain of the common source transistor M 2 ; a capacitor C 1 having one end coupled to a drain of the common source transistor M 1 and a second end coupled to a gate of the common source transistor M 2 and to a source of the common gate transistor M 3 , wherein a signal amplified by the common source transistor M 1 is amplified after being coupled by capacitor C 1 and then being applied to the gate of the common source transistor M 2 , a third-order intermodulation output of transistors M 2 and M 3 have opposite polarity to each other so that a total third-order intermodulation is cancelled at said connection between the drains of the transistors M 2 and M 3 , and the transistors M 1 , M 2 , and M 3 share a bias current.
Claim 2
Dependent Claim 178 words
A low power low noise amplifier, comprising: a common source transistor M 1 ; a common source transistor M 2 ; a common gate transistor M 3 having a drain connected to a drain of the common source transistor M 2 ; a capacitor C 1 having one end coupled to a drain of the common source transistor M 1 and a second end coupled to a gate of the common source transistor M 2 and to a source of the common gate transistor M 3 , wherein a signal amplified by the common source transistor M 1 is amplified after being coupled by capacitor C 1 and then being applied to the gate of the common source transistor M 2 , a third-order intermodulation output of transistors M 2 and M 3 have opposite polarity to each other so that a total third-order intermodulation is cancelled at said connection between the drains of the transistors M 2 and M 3 , and the transistors M 1 , M 2 , and M 3 share a bias current.

References Cited (Backward Citations)

US4182992A Cited
US4366450A Cited
US4940949A Cited
US6333677B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-04-28 2006-10-28 2007-04-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-04-28 2010-10-28 2011-04-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-04-28 2014-10-28 2015-04-29 $7700.00 Window Closed / Lapsed

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