US6541712B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed multi-layer printed circuit board via
Assignee: Amphenol Corp
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Filing: 2001-12-04
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Granted: 2003-04-01
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Expires: 2021-12-04
Abstract
Abstract A multi-layer printed circuit board includes a via having a conductive upper portion, a conductive lower portion, and an electrically insulating intermediate portion between the upper and lower portions. In one embodiment, the insulating intermediate portion of the via is provided by a non-platable layer of the circuit board, as may be comprised of PTFE. Vias having a continuous conductive coating may be formed through clearance holes in the non-platable layer which are provided with a platable inner surface, either by filling the hole with a platable material, such as epoxy resin, prior to laminating the board or by chemically conditioning the non-platable material to make it platable. In a further embodiment, the as insulating intermediate portion of the via has a narrower diameter than the conductive upper and lower portions.
Inventors
- 👤 Ellen M. Gately
- 👤 Robert A. McGrath
- 👤 Mark W. Gailus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:30
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/11; H05K1/115; H05K3/00; H05K3/40; H05K3/42; H05K3/429; H05K2201/00; H05K2201/01; H05K2201/0183; H05K2201/0187; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/096; H05K2201/09645; H05K2201/09818; H05K2201/09845; H05K2201/10; H05K2201/10007; H05K2201/10189; H05K2203/00; H05K2203/02; H05K2203/0242; H05K2203/17; H05K2203/175
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
57 words
A printed circuit board comprising: a plurality of stacked dielectric layers; and a via extending through said stacked dielectric layers, said via having an upper portion with electrically conductive walls, a lower portion with electrically conductive walls, and an intermediate portion with electrically insulating walls, said intermediate portion disposed between said upper portion and said lower portion.
Claim 2
Dependent Claim
57 words
A printed circuit board comprising: a plurality of stacked dielectric layers; and a via extending through said stacked dielectric layers, said via having an upper portion with electrically conductive walls, a lower portion with electrically conductive walls, and an intermediate portion with electrically insulating walls, said intermediate portion disposed between said upper portion and said lower portion.
Claim 3
Dependent Claim
43 words
The printed circuit board of claim 1 wherein at least one of said plurality of dielectric layers has at least one non-platable region and wherein said intermediate portion of said via extends through said at least one non-platable region of said dielectric layer.
Claim 4
Dependent Claim
27 words
The printed circuit board of claim 2 wherein said at least one dielectric layer and said non-platable region of said at least one dielectric layer comprise PTFE.
Claim 5
Dependent Claim
20 words
The printed circuit board of claim 3 wherein said at least one dielectric layer has a chemically treated, platable region.
Claim 6
Dependent Claim
30 words
The printed circuit board of claim 2 wherein said at least one dielectric layer comprises epoxy resin and said non-platable region of said at least one dielectric layer comprises PTFE.
Claim 7
Dependent Claim
26 words
The printed circuit board of claim 1 wherein said intermediate portion of said via has a smaller diameter than said upper portion and said lower portion.
Claim 8
Dependent Claim
121 words
A printed circuit board comprising: a first plurality of dielectric layers; a second plurality of dielectric layers disposed over said first plurality of dielectric layers; a dielectric layer comprised of a non-platable material disposed between said first plurality of dielectric layers and said second plurality of dielectric layers; and a via extending through said first plurality of dielectric layers, said non-platable dielectric layer and said second plurality of dielectric layers, wherein a first portion of said via extending through said first plurality of dielectric layers has conductive walls, a second portion of said via extending through said second plurality of dielectric layers has conductive walls, and a third portion of said via extending through said non-platable dielectric layer has non-conductive walls.
Claim 9
Dependent Claim
121 words
A printed circuit board comprising: a first plurality of dielectric layers; a second plurality of dielectric layers disposed over said first plurality of dielectric layers; a dielectric layer comprised of a non-platable material disposed between said first plurality of dielectric layers and said second plurality of dielectric layers; and a via extending through said first plurality of dielectric layers, said non-platable dielectric layer and said second plurality of dielectric layers, wherein a first portion of said via extending through said first plurality of dielectric layers has conductive walls, a second portion of said via extending through said second plurality of dielectric layers has conductive walls, and a third portion of said via extending through said non-platable dielectric layer has non-conductive walls.
Claim 10
Dependent Claim
15 words
The printed circuit board of claim 7 wherein said non-platable material is comprised of PTFE.
Claim 11
Dependent Claim
22 words
The printed circuit board of claim 8 wherein said non-platable material further comprises at least one of glass fibers and ceramic fibers.
Claim 12
Dependent Claim
60 words
The printed circuit board of claim 7 wherein a portion of said non-platable dielectric layer is platable and wherein said printed circuit board further comprises a second via extending through said first plurality of dielectric layers, said platable portion of said non-platable dielectric layer, and said second plurality of dielectric layers, and wherein said second via has continuously conductive walls.
Claim 13
Dependent Claim
19 words
The printed circuit board of claim 10 wherein said platable portion of said non-platable dielectric layer is chemically treated.
Claim 14
Dependent Claim
30 words
The printed circuit board of claim 10 wherein said platable portion of said non-platable dielectric layer comprises a platable material inserted into a clearance hole through said non-platable dielectric layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-31 | 2006-09-30 | 2007-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-31 | 2010-09-30 | 2011-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-31 | 2014-09-30 | 2015-04-01 | $7700.00 | Window Closed / Lapsed |