Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection

Claim 2

An NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR), the SOI-NSCR comprising: a P-type well and an N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a first P + doping region and a first N + doping region in the N-type well for use as an anode of the SOI-NSCR; a second P + doping region and a second N + doping region in the P-type well for use as a cathode of the SOI-NSCR, the first P + doping region, the N-type well, the P-type well and the second N + doping region forming a lateral silicon controlled rectifier (SCR); a third N + doping region across the N-type well and the P-type well; a gate in the P-type well and the third N + doping region, the gate and the second By N + doping region forming an NMOS; and a dummy gate in the N-type well for isolating the first P + doping region and the third N + doping region.

Claim 3

The SOI-NSCR of claim 1 wherein when a positive transient voltage is applied across the anode and the cathode of the SOI-NSCR, the positive transient voltage generates a current flowing from the first P + doping region to the N-type well.

Claim 4

The SOI-NSCR of claim 2 wherein when the positive transient voltage is greater than a junction breakdown voltage of the P-type well and the third N + doping region, the junction breaks down so that the current incurred from the positive transient voltage flows across the junction and is discharged to the cathode through the second N + doping region.

Claim 5

The SOI-NSCR of claim 1 wherein when a voltage is applied to the gate of the NMOS that turns on the NMOS, a forward bias is created that causes the SOI-NSCR to turn on, and current incurred from a positive transient voltage across the anode and the cathode is discharged to the cathode across a junction of the P-type well and the third N + doping region.

Claim 6

The SOI-NSCR of claim 1 wherein the third N + doping region is used as an N trigger node, a voltage applied to the third N + doping region generating a trigger current through the N trigger node to cause the lateral SCR to enter a latch state and to quickly trigger on the SOI-NSCR, and current incurred from a positive transient voltage across the anode and the cathode is discharged to the cathode across a junction of the P-type well and the third N + doping region.

Claim 7

The SOI-NSCR of claim 1 wherein when a negative transient voltage is applied across the anode and the cathode of the SOI-NSCR, the negative transient voltage generates a current flowing from the second P + doping region to the P-type well, and a junction of the P-type well and the N-type well is forward biased so that the current incurred from the negative transient voltage flows from the N-type well to the anode through the first N + doping region.

Claim 8

The SOI-NSCR of claim 1 wherein the junction of the third N + doping region and the P-type well is utilized for reducing the trigger voltage for the SOI-NSCR device.

Claim 9

The SOI-NSCR of claim 1 wherein the junction breakdown voltage for the P-type well and the third N + doping region is lower than the junction breakdown voltage for the P-type well and the N-type well.

Claim 10

The SOI-NSCR of claim 1 wherein the SOI-NSCR further comprises at least one spacer surrounding each gate.

Claim 11

The SOI-NSCR of claim 9 wherein the SOI-NSCR further comprises a lightly doped drain (LDD) underneath each spacer.

Claim 12

The SOI-NSCR of claim 1 wherein the first P + doping region, the second P + doping region, the first N + doping region and the second N + doping region are not in contact with the isolator in the SOI substrate so that the SOI-NSCR is capable of integration in a partially-depleted SOI CMOS process.

Claim 13

The SOI-NSCR of claim 1 wherein the first P + doping region, the second P + doping region, the first N + doping region and the second N + doping region are in contact with the isolator in the SOI substrate so that the SOI-NSCR is capable of integration in a fully-depleted SOI CMOS process.

Claim 14

A PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), the SOI-PSCR comprising: a P-type well and an N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a first P + doping region and a first N + doping region in the N-type well for use as an anode of the SOI-PSCR; a second P + doping region and a second N + doping region in the P-type well for use as a cathode of the SOI-PSCR, the first P + doping region, the N-type well, the P-type well and the second N + doping region forming a lateral silicon controlled rectifier (SCR); a third P + doping region across the N-type well and the P-type well; a gate in the N-type well and the third P + doping region, the gate and the first P + doping region forming a PMOS; and a dummy gate in the P-type well for isolating the second N + doping region and the third P + doping region.

Claim 15

A PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), the SOI-PSCR comprising: a P-type well and an N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a first P + doping region and a first N + doping region in the N-type well for use as an anode of the SOI-PSCR; a second P + doping region and a second N + doping region in the P-type well for use as a cathode of the SOI-PSCR, the first P + doping region, the N-type well, the P-type well and the second N + doping region forming a lateral silicon controlled rectifier (SCR); a third P + doping region across the N-type well and the P-type well; a gate in the N-type well and the third P + doping region, the gate and the first P + doping region forming a PMOS; and a dummy gate in the P-type well for isolating the second N + doping region and the third P + doping region.

Claim 16

The SOI-PSCR of claim 13 wherein when a positive transient voltage is applied across the anode and the cathode of the SOI-PSCR, the positive transient voltage generates a current flowing from the first P + doping region to the N-type well.

Claim 17

The SOI-PSCR of claim 14 wherein when the positive transient voltage is greater than a junction breakdown voltage of the N-type well and the third P + doping region, the junction breaks down so that the current incurred from the positive transient voltage flows across the junction and is discharged to the cathode through the second N + doping region.

Claim 18

The SOI-PSCR of claim 13 wherein when a voltage is applied to the gate of the PMOS that turns on the PMOS, a forward bias is generated that turns on the SOI-PSCR, and a current incurred from a positive transient voltage across the anode and the cathode is discharged to the cathode across a junction of the N-type well and the third P + doping region.

Claim 19

The SOI-PSCR of claim 13 wherein the third P + doping region is used as a P trigger node, a voltage applied to the third P + doping region generating a trigger current through the P trigger node that causes the lateral SCR to enter a latch state and trigger on to quickly turn on the SOI-PSCR, and current incurred from a positive transient voltage applied across the anode and the cathode is discharged to the cathode across a junction of the N-type well and the third P + doping region.

Claim 20

The SOI-PSCR of claim 13 wherein when a negative transient voltage is applied across the anode and the cathode of the SOI-PSCR, the negative transient voltage generates a current flowing from the second P + doping region to the P-type well, and a junction of the P-type well and the N-type well is forward biased so that the current incurred from the negative transient voltage flows from the N-type well to the anode through the first N + doping region.

Claim 21

The SOI-PSCR of claim 13 wherein a junction of the third P + doping region and the N-type well is utilized for reducing a trigger voltage for the SOI-PSCR.

Claim 22

The SOI-PSCR of claim 13 wherein a junction breakdown voltage for the N-type well and the third P + doping region is lower than a junction breakdown voltage for the P-type well and the N-type well.

Claim 23

The SOI-PSCR of claim 13 wherein the SOI-PSCR further comprises at least one spacer surrounding each gate.

Claim 24

The SOI-PSCR of claim 21 wherein the SOI-PSCR further comprises a lightly doped drain (LDD) underneath each spacer.

Claim 25

The SOI-PSCR of claim 13 wherein the first P + doping region, the second P + doping region, the first N + doping region and the second N + doping region are not in contact with the isolator in the SOI substrate so that the SOI-PSCR is capable of integration in a partially-depleted SOI CMOS process.

Claim 26

The SOI-PSCR of claim 13 wherein the first P + doping region, the second P + doping region, the first N + doping region and the second N + doping region are in contact with the isolator in the SOI substrate so that the SOI-PSCR is capable of integration in a fully-depleted SOI CMOS process.

Claim 27

An electrostatic discharge (ESD) protection circuit adapted to electrically connect to an I/O pad, a V SS power terminal, and a V DD power terminal, the ESD protection circuit comprising: an NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR), an anode of the SOI-NSCR electrically connected to the I/O pad, a cathode of the SOX-NSCR electrically connected to the V SS power terminal; a PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), the anode of the SOI-PSCR electrically connected to the V DD power terminal, a cathode of the SOI-PSCR electrically connected to the I/O pad; a first diode, an anode of the first diode electrically connected to the V SS power terminal, a cathode of the first diode electrically connected to the I/O pad; a second diode, an anode of the second diode electrically connected to the I/O pad, a cathode of the second diode electrically connected to the V DD power terminal; a first resistor electrically connecting the I/O pad to a first dummy gate of the SOI-NSCR, and a second resistor electrically connecting the V SS power terminal to a first gate of the SOI_NSCR; and a third resistor electrically connecting the I/O pad to the second dummy gate of the SOI_PSCR, and a fourth resistor electrically connecting the V DD power terminal to the second gate of the SOI_PSCR.

Claim 28

An electrostatic discharge (ESD) protection circuit adapted to electrically connect to an I/O pad, a V SS power terminal, and a V DD power terminal, the ESD protection circuit comprising: an NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR), an anode of the SOI-NSCR electrically connected to the I/O pad, a cathode of the SOX-NSCR electrically connected to the V SS power terminal; a PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), the anode of the SOI-PSCR electrically connected to the V DD power terminal, a cathode of the SOI-PSCR electrically connected to the I/O pad; a first diode, an anode of the first diode electrically connected to the V SS power terminal, a cathode of the first diode electrically connected to the I/O pad; a second diode, an anode of the second diode electrically connected to the I/O pad, a cathode of the second diode electrically connected to the V DD power terminal; a first resistor electrically connecting the I/O pad to a first dummy gate of the SOI-NSCR, and a second resistor electrically connecting the V SS power terminal to a first gate of the SOI_NSCR; and a third resistor electrically connecting the I/O pad to the second dummy gate of the SOI_PSCR, and a fourth resistor electrically connecting the V DD power terminal to the second gate of the SOI_PSCR.

Claim 29

The ESD protection circuit of claim 25 wherein the SOI-NSCR comprises: a first P-type well and a first N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a first P + doping region and a first N + doping region in the first N-type well for use as the anode of the SOI-NSCR; a second P + doping region and a second N + doping region in the first P-type well for use as the cathode of the SOI-NSCR, the first P + doping region, the first N-type well, the first P-type well and the second N + doping region forming a lateral silicon controlled rectifier (SCR); a third N + doping region across the N-type well and the P-type well; the first gate in the first P-type well and the third N + doping region, the first gate and the second N + doping region forming an NMOS; and the first dummy gate in the first N-type well for isolating the first P + doping region and the third N + doping region.

Claim 30

The ESD protection circuit of claim 25 wherein the SOI-PSCR comprises: a second P-type well and a second N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a third P + doping region and a fourth N + doping region in the second N-type well for use as the anode of the SOI-PSCR; a fourth P + doping region and a fifth N + doping region in the second P-type well for use as the cathode of the SOI-PSCR, the third P + doping region, the second N-type well, the second P-type well and the fifth N + doping region forming a lateral silicon controlled rectifier (SCR); a fifth P + doping region across the second N-type well and the second P-type well; the second gate in the second N-type well and the fifth P + doping region, the second gate and the third P + doping region forming a PMOS; and the second dummy gate in the second P-type well for isolating the fifth N + doping region and the fifth P + doping region.

Claim 31

A power-rail ESD protection circuit for use with a power-rail, the ESD protection circuit comprising: a first inverter, the first inverter comprising an input node and an output node; a capacitor electrically connected to the input node and a V SS power terminal of the power-rail; a first resistor electrically connected to the input node and a V DD power terminal of the power-rail; a SOI_NSCR, an anode of the SOI_NSCR electrically connected to the V DD power terminal, the SOI_NSCR comprising: a first P-type well and a first N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a first P + doping region and a first N + doping region in the first N-type well for use as the anode of the SOI-NSCR; a second P + doping region and a second N + doping region in the first P-type well for use as a cathode of the SOI-NSCR, the first P + doping region, the first N-type well, the first P-type well and the second N + doping region forming a lateral SCR; a third N + doping region across the N-type well and the P-type well; a first gate in the first P-type well and the third N + doping region, the first gate and the second N + doping region forming an NMOS; and a first dummy gate in the first N-type well for isolating the first P + doping region and the third N + doping region; a diode string electrically connected between the cathode of the SOI_NSCR and the V SS power terminal; wherein the diode string is utilized to raise a holding voltage after the SOI_NSCR is turned on to prevent the SOI_NSCR from being triggered on and entering a latch up state by a noise pulse when in a normal operating mode.

Claim 32

A power-rail ESD protection circuit for use with a power-rail, the ESD protection circuit comprising: a first inverter, the first inverter comprising an input node and an output node; a capacitor electrically connected to the input node and a V SS power terminal of the power-rail; a first resistor electrically connected to the input node and a V DD power terminal of the power-rail; a SOI_NSCR, an anode of the SOI_NSCR electrically connected to the V DD power terminal, the SOI_NSCR comprising: a first P-type well and a first N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a first P + doping region and a first N + doping region in the first N-type well for use as the anode of the SOI-NSCR; a second P + doping region and a second N + doping region in the first P-type well for use as a cathode of the SOI-NSCR, the first P + doping region, the first N-type well, the first P-type well and the second N + doping region forming a lateral SCR; a third N + doping region across the N-type well and the P-type well; a first gate in the first P-type well and the third N + doping region, the first gate and the second N + doping region forming an NMOS; and a first dummy gate in the first N-type well for isolating the first P + doping region and the third N + doping region; a diode string electrically connected between the cathode of the SOI_NSCR and the V SS power terminal; wherein the diode string is utilized to raise a holding voltage after the SOI_NSCR is turned on to prevent the SOI_NSCR from being triggered on and entering a latch up state by a noise pulse when in a normal operating mode.

Claim 33

The ESD protection circuit of claim 28 further comprising a second resistor for electrically connecting the V DD power terminal to the first dummy gate to protect a gate oxide layer in the first dummy gate.

Claim 34

The ESD protection circuit of claim 28 further comprising a third resistor for electrically connecting the diode string to the first gate to protect a gate oxide layer in the first gate.

Claim 35

The ESO protection circuit of claim 28 wherein the first gate is electrically connected to the output node of the first inverter.

Claim 36

The ESD protection circuit of claim 28 wherein the third N + doping region is electrically connected to the output node of the first inventor.

Claim 37

The ESD protection circuit of claim 32 further comprising a second inverter, an input node of the second inverter electrically connected to the capacitor and the first resistor, an output node of the second inverter electrically connected to the input node of the first inverter.

Claim 38

The ESD protection circuit of claim 32 further comprising a second inverter, an input node of the second inverter electrically connected to the capacitor and the first resistor, an output node of the second inverter electrically connected to the input node of the first inverter and the first gate.

Claim 39

The ESD protection circuit of claim 32 further comprising a second inverter, an input node of the second inverter electrically connected to the capacitor and the first resistor, an output node of the second inverter electrically connected to the input node of the first inverter and the first gate, the output node of the first inverter electrically connected to the first dummy gate.

Claim 40

A power-rail ESD protection circuit for use with a power-rail, the ESD protection circuit comprising: a first inverter, the first inverter comprising an input node and an output node; a capacitor electrically connected to the input node and a V SS power terminal of the power-rail; a first resistor electrically connected to the input node and a V DD power terminal of the power-rail; a SOI_PSCR, an anode of the SOI_PSCR electrically connected to the V DD power terminal, the SOI_PSCR comprising: a second P-type well and a second N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a third P + doping region and a fourth N + doping region in the second N-type well for use as the anode of the SOI-PSCR; a fourth P + doping region and a fifth N + doping region in the second P-type well for use as a cathode of the SOI-PSCR, the third P + doping region, the second N-type well, the second P-type well and the fifth N + doping region forming a lateral SCR; a fifth P + doping region across the second N-type well and the second P-type well; a second gate in the second N well and the fifth P + doping region, the second gate and the third P + doping region forming a PMOS; and a second dummy gate in the second P-type will for isolating the fifth N + doping region and the fifth P + doping region; a diode string electrically connected between the cathode of the SOI_PSCR and the V SS power terminal; wherein the diode string is utilized to raise a holding voltage after the SOI_PSCR is turned on to prevent the SOI_PSCR from being triggered on and entering a latch up state by a noise pulse when in a normal operating mode.

Claim 41

A power-rail ESD protection circuit for use with a power-rail, the ESD protection circuit comprising: a first inverter, the first inverter comprising an input node and an output node; a capacitor electrically connected to the input node and a V SS power terminal of the power-rail; a first resistor electrically connected to the input node and a V DD power terminal of the power-rail; a SOI_PSCR, an anode of the SOI_PSCR electrically connected to the V DD power terminal, the SOI_PSCR comprising: a second P-type well and a second N-type well in a substantially single crystal silicon layer on a surface of a silicon-on-insulator substrate; a third P + doping region and a fourth N + doping region in the second N-type well for use as the anode of the SOI-PSCR; a fourth P + doping region and a fifth N + doping region in the second P-type well for use as a cathode of the SOI-PSCR, the third P + doping region, the second N-type well, the second P-type well and the fifth N + doping region forming a lateral SCR; a fifth P + doping region across the second N-type well and the second P-type well; a second gate in the second N well and the fifth P + doping region, the second gate and the third P + doping region forming a PMOS; and a second dummy gate in the second P-type will for isolating the fifth N + doping region and the fifth P + doping region; a diode string electrically connected between the cathode of the SOI_PSCR and the V SS power terminal; wherein the diode string is utilized to raise a holding voltage after the SOI_PSCR is turned on to prevent the SOI_PSCR from being triggered on and entering a latch up state by a noise pulse when in a normal operating mode.

Claim 42

The ESD protection circuit of claim 36 further comprising a fourth resistor for electrically connecting the diode string to the second dummy gate to protect a gate oxide layer in the second dummy gate.

Claim 43

The ESD protection circuit of claim 36 further comprising a fifth resistor for electrically connecting the V DD power terminal to the second gate to protect a gate oxide layer in the second gate.

Claim 44

The ESD protection circuit of claim 36 wherein the second gate is electrically connected to the output node of the first inverter.

Claim 45

The ESD protection circuit of claim 39 further comprises a third inverter, an input node of the third inverter electrically connected to the capacitor and the first resistor, an output node of the third inverter electrically connected to the input node of the first inverter.

Claim 46

The ESD protection circuit of claim 36 wherein the fifth P + doping region is electrically connected to the output node of the first inverter.

Claim 47

The ESD protection circuit of claim 41 further comprising a third inverter, an input node of the third inverter electrically connected to the output node of the first inverter, an output node of the third inverter electrically connected to the second gate.

Claim 48

An electrostatic discharge (ESD) protection circuit adapted to electrically connect to an pad, a V SS power terminal, and a V DD power terminal, the ESD protection circuit comprising: an NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR), an anode of the SOI-NSCR electrically connected to the I/O pad, a cathode of the SOI-NSCR electrically connected to the V SS power terminal; a PMOS-trigger silicon controlled rectifier in Bilicon-on-insulator (SOI-PSCR), the anode of the SOI-PSCR electrically connected to the V DD power terminal, a cathode of the SOI-PSCR electrically connected to the I/O pad; a first diode, an anode of the first diode electrically connected to the V SS power terminal, a cathode of the first diode electrically connected to the I/O pad; a second diode, an anode of the second diode electrically connected to the I/O pad, a cathode of the second diode electrically connected to the V DD power terminal; a first resistor electrically connecting the I/O pad to a first dummy gate of the SOI-NSCR, and a second resistor electrically connecting the V SS power terminal to a first gate of the SOI_NSCR; and a third resistor electrically connecting the I/O pad to the second dummy gate of the SOI_PSCR, and a fourth resistor electrically connecting the V DD power terminal to the second gate of the SOI_PSCR; wherein when appositive-to-V SS ESD voltage is applied to the I/O pad, the SOI_NSCR is turned on to discharge ESD current to the V SS power terminal, when a negative-to-V SS ESD voltage is applied to the I/O pad, the first diode is turned on to discharge ESD current to the V SS power terminal, when a negative-to-V DD ESD voltage is applied to the I/O pad, the SOI-PSCR is turned on to discharge ESD current to the V DD power terminal, when a positive-to-V DD ESD voltage is applied to the I/O pad, the second diode is turned on to discharge ESD current to the V DD power terminal, and when the ESD protection circuit is under a normal operating mode, the SOI-PSCR, the SOI-NSCR, the first diode and the second diode are all turned off.

Claim 49

An electrostatic discharge (ESD) protection circuit adapted to electrically connect to an pad, a V SS power terminal, and a V DD power terminal, the ESD protection circuit comprising: an NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR), an anode of the SOI-NSCR electrically connected to the I/O pad, a cathode of the SOI-NSCR electrically connected to the V SS power terminal; a PMOS-trigger silicon controlled rectifier in Bilicon-on-insulator (SOI-PSCR), the anode of the SOI-PSCR electrically connected to the V DD power terminal, a cathode of the SOI-PSCR electrically connected to the I/O pad; a first diode, an anode of the first diode electrically connected to the V SS power terminal, a cathode of the first diode electrically connected to the I/O pad; a second diode, an anode of the second diode electrically connected to the I/O pad, a cathode of the second diode electrically connected to the V DD power terminal; a first resistor electrically connecting the I/O pad to a first dummy gate of the SOI-NSCR, and a second resistor electrically connecting the V SS power terminal to a first gate of the SOI_NSCR; and a third resistor electrically connecting the I/O pad to the second dummy gate of the SOI_PSCR, and a fourth resistor electrically connecting the V DD power terminal to the second gate of the SOI_PSCR; wherein when appositive-to-V SS ESD voltage is applied to the I/O pad, the SOI_NSCR is turned on to discharge ESD current to the V SS power terminal, when a negative-to-V SS ESD voltage is applied to the I/O pad, the first diode is turned on to discharge ESD current to the V SS power terminal, when a negative-to-V DD ESD voltage is applied to the I/O pad, the SOI-PSCR is turned on to discharge ESD current to the V DD power terminal, when a positive-to-V DD ESD voltage is applied to the I/O pad, the second diode is turned on to discharge ESD current to the V DD power terminal, and when the ESD protection circuit is under a normal operating mode, the SOI-PSCR, the SOI-NSCR, the first diode and the second diode are all turned off.