Method for simulating noise on the input of a static gate and determining noise on the output

Claim 3

The method as in claim 1 wherein the FETs of a first type are PFETs.

Claim 4

The method as in claim 1 wherein the FETs of a second type are NFETs.

Claim 5

The method as in claim 1 wherein the FETs of a first type are PFETs and the FETs of a second type are NFETs.

Claim 6

The method as in claim 4 wherein a maximum P/N value is calculated.

Claim 7

The method as in claim 4 wherein a minimum P/N value is calculated.

Claim 8

A computer-readable medium having computer-executable instructions for performing a method for simulating noise on an input of a static gate and determining noise on an output of the gate comprising: a) identifying directly-connected FETs of a first type connected to an output node; b) identifying directly-connected FETs of a second type connected to said output node; c) identifying branches of a first type created by said first type FETs connected to said output node; d) identifying branches of a second type created by said second type FETs connected to said output node; e) selecting an allowable input voltage; f) storing width values of all said first type FETs activated by said chosen input values; g) storing width values of all said second type FETs activated by said chosen input values; h) determining an effective width of said stored width values in step (f); i) determining an effective width of said stored width values in step (g); j) dividing the effective width in step (h) by the effective width in step (i); k) repeating steps (e) through (j) until all possible input voltage combinations have been exhausted; l) choosing a P/N ratio from the combinations; m) simulating noise on an input of said P/N ratio; n) determining noise created on an output of said P/N ratio.

Claim 9

A computer-readable medium having computer-executable instructions for performing a method for simulating noise on an input of a static gate and determining noise on an output of the gate comprising: a) identifying directly-connected FETs of a first type connected to an output node; b) identifying directly-connected FETs of a second type connected to said output node; c) identifying branches of a first type created by said first type FETs connected to said output node; d) identifying branches of a second type created by said second type FETs connected to said output node; e) selecting an allowable input voltage; f) storing width values of all said first type FETs activated by said chosen input values; g) storing width values of all said second type FETs activated by said chosen input values; h) determining an effective width of said stored width values in step (f); i) determining an effective width of said stored width values in step (g); j) dividing the effective width in step (h) by the effective width in step (i); k) repeating steps (e) through (j) until all possible input voltage combinations have been exhausted; l) choosing a P/N ratio from the combinations; m) simulating noise on an input of said P/N ratio; n) determining noise created on an output of said P/N ratio.

Claim 10

The medium as in claim 7 wherein the FETs of a first type are PFETs.

Claim 11

The medium as in claim 7 wherein the FETs of a second type are NFETs.

Claim 12

The medium as in claim 7 wherein the FETs of a first type are PFETs and the FETs of a second type are NFETs.

Claim 13

The medium as in claim 10 wherein a maximum P/N value is calculated.

Claim 14

The medium as in claim 10 wherein a minimum P/N value is calculated.

Claim 15

A computer system for calculating P/N ratios in static logic gates in a circuit design comprising: a) a storage medium; b) a software program stored on the storage medium for calculating P/N ratios in static logic gates in circuit designs, said software comprising a set of instructions for: 1) identifying directly-connected FETs of a first type connected to an output node; 2) identifying directly-connected FETs of a second type connected to said output node; 3) identifying branches of a first type created by said first type FETs connected to said output node; 4) identifying branches of a second type created by said second type FETs connected to said output node; 5) selecting an allowable input voltage; 6) storing width values of all said first type FETs activated by said chosen input values; 7) storing width values of all said second type FETs activated by said chosen input values; 8) determining an effective width of said stored width values in step (6); 9) determining an effective width of said stored width values in step (7); 10) dividing the effective width in step (8) by the effective width in step (9); 11) repeating steps (5) through (10) until all possible input voltage combinations have been exhausted; 12) choosing a P/N ratio from the combinations; 13) simulating noise on an input of said P/N ratio; 14) determining noise created on an output of said P/N ratio.

Claim 16

A computer system for calculating P/N ratios in static logic gates in a circuit design comprising: a) a storage medium; b) a software program stored on the storage medium for calculating P/N ratios in static logic gates in circuit designs, said software comprising a set of instructions for: 1) identifying directly-connected FETs of a first type connected to an output node; 2) identifying directly-connected FETs of a second type connected to said output node; 3) identifying branches of a first type created by said first type FETs connected to said output node; 4) identifying branches of a second type created by said second type FETs connected to said output node; 5) selecting an allowable input voltage; 6) storing width values of all said first type FETs activated by said chosen input values; 7) storing width values of all said second type FETs activated by said chosen input values; 8) determining an effective width of said stored width values in step (6); 9) determining an effective width of said stored width values in step (7); 10) dividing the effective width in step (8) by the effective width in step (9); 11) repeating steps (5) through (10) until all possible input voltage combinations have been exhausted; 12) choosing a P/N ratio from the combinations; 13) simulating noise on an input of said P/N ratio; 14) determining noise created on an output of said P/N ratio.

Claim 17

The computer system as in claim 13 wherein the FETs of a first type are PFETs.

Claim 18

The computer system as in claim 13 wherein the FETs of a second type are NFETs.

Claim 19

The computer system as in claim 13 wherein the FETs of a first type are PFETs and the FETs of a second type are NFETs.

Claim 20

The computer system as in claim 16 wherein a maximum P/N value is calculated.

Claim 21

The computer system as in claim 16 wherein a minimum P/N value is calculated.