US6493836B2
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US
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Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices
Assignee: Mosaid Technologies Inc
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Filing: 2000-11-30
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Granted: 2002-12-10
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Expires: 2020-11-30
Abstract
Abstract A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.
Inventors
- 👤 Sompong P. Olarig
- 👤 John E. Jenne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:53
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G11C29/02; G11C29/028; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C2029/0409; G11C2029/4402
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
120 words
A computer system, comprising: a CPU; memory control logic coupled to said CPU; a system memory coupled to said memory control logic, with said memory control logic controlling and formatting transactions to the system memory; error checking logic coupled to said system memory, said error checking logic detecting the number of memory errors that occur in said system memory, and providing a signal to said memory control logic indicating the number of memory errors detected; and wherein said memory controller runs calibration cycles to said system memory to recalibrate said system memory, and wherein said memory controller is capable of varying the frequency of said calibration cycles based on the number of memory errors detected by said error checking logic.
Claim 2
Dependent Claim
120 words
A computer system, comprising: a CPU; memory control logic coupled to said CPU; a system memory coupled to said memory control logic, with said memory control logic controlling and formatting transactions to the system memory; error checking logic coupled to said system memory, said error checking logic detecting the number of memory errors that occur in said system memory, and providing a signal to said memory control logic indicating the number of memory errors detected; and wherein said memory controller runs calibration cycles to said system memory to recalibrate said system memory, and wherein said memory controller is capable of varying the frequency of said calibration cycles based on the number of memory errors detected by said error checking logic.
Claim 3
Dependent Claim
18 words
The system of claim 1 , wherein said error checking logic is integrated with said memory control logic.
Claim 4
Dependent Claim
16 words
The system of claim 2 , wherein said error checking logic further includes error correction logic.
Claim 5
Dependent Claim
15 words
The system of claim 1 , wherein the calibration cycles comprise a temperature calibration cycle.
Claim 6
Dependent Claim
15 words
The system of claim 1 , wherein the calibration cycles comprise a current calibration cycle.
Claim 7
Dependent Claim
16 words
The system of claim 1 , wherein the system memory comprises a plurality of RDRAM devices.
Claim 8
Dependent Claim
30 words
The system of claim 6 , wherein said system memory is configured into a plurality of memory channels, and wherein separate error checking logic is provided for each memory channel.
Claim 9
Dependent Claim
40 words
The system of claim 7 , wherein the memory controller logic is capable of independently changing the calibration frequency on a channel-by-channel basis, based on the number of memory errors detected by the error checking logic associated with each channel.
Claim 10
Dependent Claim
19 words
The system of claim 8 , wherein the memory control logic includes a RAC associated with each memory channel.
Claim 11
Dependent Claim
60 words
The system of claim 9 , wherein the memory control logic includes at least one calibration timer associated with each RAC, and said memory control logic changes the calibration frequency for each channel by modifying the value of the calibration timer associated with a particular RAC, to thereby modify the calibration frequency of the memory channel associated with that RAC.
Claim 12
Dependent Claim
27 words
The system of claim 1 , wherein the memory control logic increases the calibration frequency if the number of detected memory errors is above a threshold value.
Claim 13
Dependent Claim
27 words
The system of claim 11 , wherein the memory control logic decreases the calibration frequency if the number of detected memory errors is below a threshold value.
Claim 14
Dependent Claim
27 words
The system of claim 1 , wherein the memory control logic decreases the calibration frequency if the number of detected memory errors is below a threshold value.
Claim 15
Dependent Claim
92 words
A computer system, comprising: a CPU; a system memory comprising a plurality of DRAM memory devices coupled to said CPU; a memory controller coupling said system memory to said CPU, said memory controller controlling and formatting transactions to the DRAM memory devices, and wherein said memory controller monitors the system memory for memory errors; and wherein said memory controller periodically runs calibration cycles to said DRAM memory devices, and wherein said memory controller modifies the frequency of at least one of said calibration cycles in response to detection of said memory errors.
Claim 16
Dependent Claim
92 words
A computer system, comprising: a CPU; a system memory comprising a plurality of DRAM memory devices coupled to said CPU; a memory controller coupling said system memory to said CPU, said memory controller controlling and formatting transactions to the DRAM memory devices, and wherein said memory controller monitors the system memory for memory errors; and wherein said memory controller periodically runs calibration cycles to said DRAM memory devices, and wherein said memory controller modifies the frequency of at least one of said calibration cycles in response to detection of said memory errors.
Claim 17
Dependent Claim
17 words
The system of claim 14 , wherein said high-speed DRAM memory devices comprise Direct RDRAM memory devices.
Claim 18
Dependent Claim
15 words
The system of claim 14 , wherein the calibration cycles comprise a temperature calibration cycle.
Claim 19
Dependent Claim
15 words
The system of claim 14 , wherein the calibration cycles comprise a current calibration cycle.
Claim 20
Dependent Claim
31 words
The system of claim 14 , wherein said memory controller monitors the number of memory errors and modifies the calibration frequency when the number of memory errors exceeds a threshold value.
Claim 21
Dependent Claim
29 words
The system of claim 14 , wherein said memory controller monitors the number and frequency of memory errors and modifies the calibration frequency when a threshold value is exceeded.
Claim 22
Dependent Claim
32 words
The system of claim 14 , wherein said memory controller monitors the number of memory errors and modifies the calibration frequency when the number of memory errors is below a threshold value.
Claim 23
Dependent Claim
31 words
The system of claim 14 , wherein the memory controller monitors the number and frequency of memory errors and modifies the calibration frequency when a threshold error value is not met.
Claim 24
Dependent Claim
44 words
The system of claim 14 , wherein the memory controller includes error checking logic that detects errors in the system memory, and said memory controller further includes control logic that receives signals from the error checking logic, and in response, changes the calibration frequency.
Claim 25
Dependent Claim
30 words
The system of claim 22 , wherein the system memory comprises a plurality of RDRAM devices arranged in multiple channels, and wherein error checking logic is associated with each channel.
Claim 26
Dependent Claim
152 words
A computer system, comprising: a CPU; a memory controller coupled to said CPU; a video controller coupled to said memory controller; an I/O controller hub coupled to said memory controller, said I/O controller hub connecting to at least one peripheral bus for coupling to a peripheral device; a system memory comprised of multiple DRAM memory devices arranged in a plurality of channels, each of which is coupled to said memory controller, with said memory controller controlling and formatting transactions to the DRAM memory devices originating from said CPU and other computer system components, including said peripheral device; wherein said memory controller runs calibration cycles to said DRAM memory devices to re-calibrate said memory devices, and wherein said memory controller is capable of varying the frequency of said calibration cycles on a channel-by-channel basis based on the number of memory errors that occur in said DRAM memory devices located on a particular channel.
Claim 27
Dependent Claim
152 words
A computer system, comprising: a CPU; a memory controller coupled to said CPU; a video controller coupled to said memory controller; an I/O controller hub coupled to said memory controller, said I/O controller hub connecting to at least one peripheral bus for coupling to a peripheral device; a system memory comprised of multiple DRAM memory devices arranged in a plurality of channels, each of which is coupled to said memory controller, with said memory controller controlling and formatting transactions to the DRAM memory devices originating from said CPU and other computer system components, including said peripheral device; wherein said memory controller runs calibration cycles to said DRAM memory devices to re-calibrate said memory devices, and wherein said memory controller is capable of varying the frequency of said calibration cycles on a channel-by-channel basis based on the number of memory errors that occur in said DRAM memory devices located on a particular channel.
Claim 28
Dependent Claim
107 words
The system as in claim 24 , wherein said memory controller includes: error checking logic associated with each channel that detects memory errors that occur during transactions to said memory devices in that channel; a calibration timer associated with each channel that stores a timer value that determines the frequency of at least one calibration cycle; and control logic that receives a signal from each of said error checking logic identifying the number of memory errors detected in the associated channel, and in response, is capable of transmitting a signal to the associated calibration timer for that channel to change the timer value stored in said timer.
Claim 29
Dependent Claim
131 words
A computer system, comprising: a CPU; a memory controller coupled to said CPU; an I/O controller coupled to said memory controller, said I/O controller connecting to at least one peripheral bus for coupling to a peripheral device; a system memory comprised of multiple DRAM memory devices arranged in at least one channel that couples to said memory controller, with said memory controller controlling and formatting transactions to the DRAM memory devices originating from said CPU and other computer system components, including said peripheral device; wherein said memory controller runs calibration cycles to said DRAM memory devices to re-calibrate said memory devices, and wherein said memory controller is capable of varying the frequency of said calibration cycles based on the number of errors that occur during transactions to said DRAM memory devices.
Claim 30
Dependent Claim
131 words
A computer system, comprising: a CPU; a memory controller coupled to said CPU; an I/O controller coupled to said memory controller, said I/O controller connecting to at least one peripheral bus for coupling to a peripheral device; a system memory comprised of multiple DRAM memory devices arranged in at least one channel that couples to said memory controller, with said memory controller controlling and formatting transactions to the DRAM memory devices originating from said CPU and other computer system components, including said peripheral device; wherein said memory controller runs calibration cycles to said DRAM memory devices to re-calibrate said memory devices, and wherein said memory controller is capable of varying the frequency of said calibration cycles based on the number of errors that occur during transactions to said DRAM memory devices.
Claim 31
Dependent Claim
86 words
The system as in claim 26 , wherein said memory controller includes: error checking logic that detects memory errors that occur during transactions to said memory devices; a calibration timer that stores a timer value that determines the frequency of at least one calibration cycle; and control logic that receives a signal from said error checking logic identifying the number of memory errors detected, and in response, is capable of transmitting a signal to said calibration timer to change the timer value stored in said timer.
Claim 32
Independent Claim
57 words
A method of modifying the frequency of a calibration cycle in a memory controller, comprising: detecting the number of memory errors that occur in a memory channel; determining if the number of memory errors exceeds a predetermined threshold value; and increasing the frequency of the calibration cycle if the number of memory errors exceeds the threshold value.
Claim 33
Independent Claim
57 words
A method of modifying the frequency of a calibration cycle in a memory controller, comprising: detecting the number of memory errors that occur in a memory channel; determining if the number of memory errors exceeds a predetermined threshold value; and increasing the frequency of the calibration cycle if the number of memory errors exceeds the threshold value.
Claim 34
Dependent Claim
42 words
A method as in claim 28 , further comprising: determining if the number of memory errors is below a second threshold value; and decreasing the frequency of the calibration cycle if the number of memory errors is below the second threshold value.
Claim 35
Dependent Claim
23 words
A method as in claim 29 , wherein the frequency of the calibration cycle is only decreased down to a minimum frequency value.
Claim 36
Dependent Claim
28 words
A method as in claim 29 , wherein the act of decreasing the frequency of the calibration cycle includes increasing a timer value stored in a calibration timer.
Claim 37
Dependent Claim
23 words
A method as in claim 28 , wherein the frequency of the calibration cycle is only increased up to a maximum frequency value.
Claim 38
Dependent Claim
28 words
A method as in claim 28 , wherein the act of increasing the frequency of the calibration cycle includes decreasing a timer value stored in a calibration timer.
References Cited (Backward Citations)
US5084791A
Cited
US6373768B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-09 | 2006-06-10 | 2006-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-09 | 2010-06-10 | 2010-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-09 | 2014-06-10 | 2014-12-10 | $7700.00 | Window Closed / Lapsed |