Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region

Claim 2

A latch-up verifying method, comprising the steps of: extracting a well region, at least one transistor region, and at least one substrate contact region from layout data of a semiconductor integrated circuit to be formed on a semiconductor substrate; sequentially executing steps for separately setting respective over-sizing values for at least two of the transistor and substrate contact regions based upon the extracted information; and executing latch-up verification of the layout data utilizing the separately set over-sizing values.

Claim 3

A latch-up verifying method according to claim 1 , wherein said method includes a step for forming a database used to store over-sizing values; said extracting step includes a first extraction step for extracting a well region from said layout data, a second extraction step for extracting the at least one transistor region from said layout data, and a third extraction step for extracting the at least one substrate contact region from said layout data; wherein said steps of setting over-sizing values includes determining an over-sizing value based upon said extracted information obtained from said first extraction step to said third extraction step; said method further includes a step for defining an over-sized region based upon said determined over-sizing value; and said step of executing the latch-up verification includes checking as to whether or not the transistor region is contained within the over-sized region defined at said definition step.

Claim 4

A latch-up verifying method according to claim 2 , wherein: said over-sizing determination step is arranged by determining the over-sizing value based upon one of a structural condition and a use condition of the at least one transistor region of said semiconductor integrated circuit.

Claim 5

A latch-up verifying method according to claim 3 , wherein: said over-sizing determination step is arranged by determining the over-sizing value based upon a position relationship among said at least one transistor region, said well region, and said at least one substrate contact region.

Claim 6

A latch-up verifying method according to claim 4 , wherein: said over-sizing determination step is arranged by determining the over-sizing value based upon a distance defined between said well region and said at least one transistor region.

Claim 7

A latch-up verifying method according to claim 4 , wherein: said over-sizing determination step is arranged by determining the over-sizing value based upon a distance defined between said well region and said at least one substrate contact region.

Claim 8

A latch-up verifying method according to claim 3 , wherein: said over-sizing determination step is arranged by determining the over-sizing value, while considering a dimension of the at least one transistor region.

Claim 9

A latch-up verifying method according to claim 3 , wherein: said over-sizing determination step is arranged by determining the over-sizing value, while considering a gate length and/or a gate width of the at least one transistor region.

Claim 10

A latch-up verifying method according to claim 3 , wherein: said over-sizing determination step is arranged by determining the over-sizing value in correspondence with a current capability of said at least one transistor region of said semiconductor integrated circuit.

Claim 11

A latch-up verifying method according to claim 3 , wherein: said semiconductor integrated circuit is equipped with a salicide wiring structure; said at least one substrate contact region is constituted by a via-hole-containing contact region for contacting through a via-hole within said semiconductor substrate, and a surface contact region formed on a surface of the semiconductor substrate, while does not contact through a via-hole within said semiconductor substrate; and said over-sizing determining step judges as to whether said at least one substrate contact region is the via-hole-containing contact region, or the surface contact region, and is arranged by reducing the over-sizing value in the case that said substrate contact region is the surface contact region.

Claim 12

A latch-up verifying method according to claim 1 , wherein: said step of setting over-sizing values includes the use of a function wherein one of a structural characteristic and an electric characteristic of the at least one transistor region of said semiconductor integrated circuit is used as a parameter.

Claim 13

A latch-up verifying method according to claim 1 , wherein: said steps of setting over-sizing values includes the use of a table containing a parameter made of one of a structural characteristic and an electric characteristic of each of the at least one transistor region of said semiconductor integrated circuit.

Claim 14

A latch-up verifying method according to claim 1 , wherein: one over-sizing value along a horizontal direction is made different from another over-sizing value along a vertical direction.

Claim 15

A latch-up verifying method according to claim 1 , wherein: an over-sizing value at a right hand along a horizontal direction is made different from an over-sizing value at a left hand along said horizontal direction.

Claim 16

A latch-up verifying method according to claim 1 , wherein: an over-sizing value at an upper hand along a vertical direction is made different from an over-sizing value at a lower hand along the vertical direction.

Claim 17

A latch-up verifying apparatus including: means for extracting a well region, at least one transistor region, and at least one substrate contract region from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and means for sequentially, separately setting over-sizing values for at least two of the transistor and substrate contact regions based upon the extracted information; and means for executing latch-up verification of the layout data utilizing the separately set over-sizing values.

Claim 18

A latch-up verifying apparatus including: means for extracting a well region, at least one transistor region, and at least one substrate contract region from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and means for sequentially, separately setting over-sizing values for at least two of the transistor and substrate contact regions based upon the extracted information; and means for executing latch-up verification of the layout data utilizing the separately set over-sizing values.

Claim 19

A latch-up verifying apparatus according to claim 16 , wherein: said apparatus further includes a database used to store over-sizing values; said means for extracting including first extraction means for extracting a well region from said layout data, second extraction means for extracting the at least one transistor region from said layout data, and third extraction means for extracting the at least one substrate contact region from said layout data; said means for setting over-sizing values includes determination means for determining an over-sizing value based upon said extracted information obtained from said first extraction means to said third extraction means; said apparatus further includes definition means for defining an over-sizing region based upon said determined over-sizing value; and said means for executing the latch-up verification includes means for checking as to whether or not the transistor region is contained within the over-sizing region defined at said definition means.

Claim 20

A latch-up verifying apparatus according to claim 17 , wherein: said determination means is arranged by determining the over-sizing value based upon any one of a structural condition and a use condition of the at least one transistor region of said semiconductor integrated circuit.

Claim 21

A latch-up verifying apparatus according to claim 18 , wherein: said determination means is arranged by determining the over-sizing value based upon a position relationship among said at least one transistor region, said well region, and said at least one substrate contact region.

Claim 22

A latch-up verifying apparatus according to claim 19 , wherein: said determining means is arranged by determining the over-sizing value based upon a distance defined between said well region and said at least one transistor region.

Claim 23

A latch-up verifying apparatus according to claim 19 , wherein: said determination means is arranged by determining the over-sizing value based upon a distance defined between said well region and said at least one substrate contact region.

Claim 24

A latch-up verifying apparatus according to claim 18 , wherein: said determination means is arranged by determining the over-sizing value, while considering a dimension of the at least one transistor region.

Claim 25

A latch-up verifying apparatus according to claim 17 , wherein: said determination means is arranged by determining the over-sizing value, while considering a gate length and/or a gate width of the at least one transistor region.

Claim 26

A latch-up verifying apparatus according to claim 17 , wherein: said determination means is arranged by determining the over-sizing value in correspondence with a current capability of each of said at least one transistor region of said semiconductor integrated circuit.

Claim 27

A latch-up verifying apparatus according to claim 16 , wherein: said over-sizing value database is constituted by a function that one of a structural characteristic and an electric characteristic of the at least one transistor region of said semiconductor integrated circuit is used as a parameter; and the over sizing value is determined by said function.

Claim 28

A latch-up verifying apparatus according to claim 16 , wherein: said over-sizing value database is constituted by a table containing a parameter made of one of a structural characteristic and electrical characteristic of the at least one transistor regions of said semiconductor integrated circuit; and the over-sizing value is determined by said table.