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US6486492B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated critical dimension control for semiconductor device manufacturing

Assignee: Applied Materials Inc
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Filing: 2000-11-20
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Granted: 2002-11-26
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Expires: 2020-11-20
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Abstract

Abstract A method and apparatus for reducing lot to lot CD variation in semiconductor wafer processing feeds back information gathered during inspection of a wafer, such as after photoresist application, exposure and development, to upcoming lots that will be going through the photolithography process, and feeds forward information to adjust the next process the inspected wafer will undergo (e.g., the etch process). Embodiments include forming a feature such as an etch mask on a semiconductor wafer at a “photo cell” by a photolithography process, then conventionally imaging the feature with a CD-SEM to measure its CD and other sensitive parameters. The measured parameters are linked, via the feature's SEM waveform, to photolithography adjustable parameters such as stepper focus and exposure settings. If the measured parameters deviate from design dimensions, the linked information on focus and exposure is fed back to the photo cell so the stepper can be adjusted, either automatically or at the user's discretion, to correct the deviation in following lots. The measured parameters are also linked to etch process adjustable parameters such as etch recipes for different over-etch and/or etch chemistry. If the measured parameters deviate from desired values, a linked etch recipe to correct the error is fed forward to the etcher and implemented automatically or at the user's discretion. This feedback and feed-forward mechanism improves lot to lot CD control at inspection following photoresist development and at final inspection as well.

Inventors

  • 👤 Bo Su

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 04:17
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/7055; G03F7/70558; H; H10; H10P; H10P74/00; G03F7/70605; G03F7/70616; G03F7/70625; G03F7/70641; H10P72/00; H10P72/06; H10P72/0604; H10P74/23

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 140 words
An apparatus for controlling the processing of a semiconductor wafer, comprising: an imager for obtaining a CD of a target feature on the wafer, the target feature formed using a first process, and for producing a target waveform corresponding to the target feature; a storage medium that stores: the target further CD and the target waveform; and a plurality of reference waveforms corresponding to a plurality of reference features on a reference semiconductor wafer, the reference features having a CD and a waveform comparable to the target feature CD and target waveforms, each of the reference features respectively associated with a different known set of second process parameter values; and a processor configured to identify the reference waveform that most closely matches the target waveform to obtain the second process parameter values for performing a second process on the wafer.
Claim 2
Independent Claim 140 words
An apparatus for controlling the processing of a semiconductor wafer, comprising: an imager for obtaining a CD of a target feature on the wafer, the target feature formed using a first process, and for producing a target waveform corresponding to the target feature; a storage medium that stores: the target further CD and the target waveform; and a plurality of reference waveforms corresponding to a plurality of reference features on a reference semiconductor wafer, the reference features having a CD and a waveform comparable to the target feature CD and target waveforms, each of the reference features respectively associated with a different known set of second process parameter values; and a processor configured to identify the reference waveform that most closely matches the target waveform to obtain the second process parameter values for performing a second process on the wafer.
Claim 3
Dependent Claim 31 words
The apparatus of claim 1 , wherein the processor is further configured to cause the second process to be performed on the wafer based on the obtained second process parameter values.
Claim 4
Dependent Claim 50 words
The apparatus of claim 2 , wherein the second process is an etch process and the second process parameter values comprise etch recipes for adjusting the target feature CD during the second process; wherein the processor is further configured to cause the second process to adjust the target feature CD.
Claim 5
Dependent Claim 68 words
The apparatus of claim 1 , wherein the processor is further configured to: select one of the reference waveforms as a golden waveform; compare the target waveform with the golden waveform; and compare the target waveform to other reference waveforms to identify the reference waveform that most closely matches the target waveform when the target waveform deviates from the golden waveform by more than a predetermined threshold amount.
Claim 6
Dependent Claim 58 words
The apparatus of claim 3 , wherein each reference feature is further associated with a different known set of first process parameter values; and wherein the processor is further configured to obtain the first process parameter values associated with the reference waveform that most closely matches the target waveform for performing the first process on another semiconductor wafer.
Claim 7
Dependent Claim 32 words
The apparatus of claim 5 , wherein the processor is further configured to cause the first process to be performed on the other wafer responsive to the obtained first process parameter values.
Claim 8
Dependent Claim 65 words
The apparatus of claim 6 , wherein the first process is performed on the wafer using a set of initial first process parameter values; and wherein the processor is further configured to cause the first process to be performed on the other wafer using the initial first process parameter values when the target waveform deviates from the golden waveform less than the predetermined threshold amount.
Claim 9
Dependent Claim 26 words
The apparatus of claim 6 , wherein the first process is a photolithographic process and the first process parameter values comprise stepper focus and exposure settings.
Claim 10
Dependent Claim 15 words
The apparatus of claim 1 , wherein the imager is a scanning electron microscope (SEM).
Claim 11
Dependent Claim 15 words
The apparatus of claim 1 , wherein the storage medium is a digital storage device.
Claim 12
Dependent Claim 133 words
The apparatus of claim 5 , wherein the wafer has a plurality of features, one feature being at a selected location on the wafer; wherein the imager is for obtaining CDs and for producing target waveforms corresponding to more than one of the plurality of features, including the feature at the selected location; and wherein the processor is further configured to compare the CDs of the target features to a predetermined nominal CD value, and cause the first process to be performed on the other semiconductor wafer responsive to the first process parameter values associated with the reference waveform that most closely matches the target waveform of the feature at the selected location when the CD of one of the target features deviates from the nominal CD value more than a predetermined amount.
Claim 13
Dependent Claim 73 words
The apparatus of claim 11 , wherein the processor is further configured to: average the CDs of the target features to obtain an average CD; and identify the reference waveform associated with a CD that most closely matches the average CD to obtain the second process parameter values for performing the second process when the CD of one of the target features deviates from the nominal CD value more than a predetermined amount.

References Cited (Backward Citations)

US4447731A Cited
JPS61290312A Cited
US5109430A Cited
EP0727715A1 Cited
US5926690A Cited
US6054710A Cited
US6245581B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2005-11-25 2006-05-27 2006-11-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2009-11-25 2010-05-27 2010-11-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2013-11-25 2014-05-27 2014-11-26 $7700.00 Window Closed / Lapsed

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