US6463575B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cell-layout method in integrated circuit devices
Assignee: Mitsubishi Electric Corp
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Filing: 2000-01-28
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Granted: 2002-10-08
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Expires: 2020-01-28
Abstract
Abstract A cell-layout method comprises the steps of: establishing cut lines in vertical and horizontal directions for substrate division; assuming an entire substrate as one cell-layout region and assigning all cells of an integrated circuit to the region; defining a set of the cells within the cell-layout region; determining a direction of the cut line to division-process the cell-layout region; selecting one cut line per row or column of non-processed cut lines in the horizontal or vertical direction based on the determined direction; determining a cell in the cell-layout region by implementing a Min-Cut division in cluster unit to the selected cut line, and implementing the division in parallel for a plurality of cut lines, thereby determining cells to be placed on the cell-layout region, with the result of cutting a process time in a large scale integrated circuit and avoiding local wire congestion.
Inventors
- 👤 Kazuhiro Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:35
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
181 words
A method of a cell-layout in an integrated circuit device, comprising: a first step of establishing a plurality of cut lines in vertical and horizontal directions to divide a substrate; a second step of considering the entire substrate as one cell-layout region and assigning all the cells included in an integrated circuit in said cell-layout region; a third step of defining as one cluster a set of a plurality of cells within said cell-layout region; a fourth step of determining a direction of the cut line to division-process said cell-layout region; a fifth step of selecting one cut line per row or column of the cell-layout region on the substrate among non-processed cut lines in the horizontal or vertical direction based on the determined direction; a sixth step of determining a cell to be placed in said cell-layout region by implementing a Min-Cut division in a cluster unit with respect to said cut line selected at said fifth step, thereby dividing the substrate into smaller regions and implementing said division in parallel with respect to a plurality of said cut lines.
Claim 2
Independent Claim
181 words
A method of a cell-layout in an integrated circuit device, comprising: a first step of establishing a plurality of cut lines in vertical and horizontal directions to divide a substrate; a second step of considering the entire substrate as one cell-layout region and assigning all the cells included in an integrated circuit in said cell-layout region; a third step of defining as one cluster a set of a plurality of cells within said cell-layout region; a fourth step of determining a direction of the cut line to division-process said cell-layout region; a fifth step of selecting one cut line per row or column of the cell-layout region on the substrate among non-processed cut lines in the horizontal or vertical direction based on the determined direction; a sixth step of determining a cell to be placed in said cell-layout region by implementing a Min-Cut division in a cluster unit with respect to said cut line selected at said fifth step, thereby dividing the substrate into smaller regions and implementing said division in parallel with respect to a plurality of said cut lines.
Claim 3
Dependent Claim
127 words
A method of a cell-layout in an integrated circuit device according to claim 1 , further comprising: a seventh step for comparing the number of the cell-layout regions with a predetermined value; an eighth step for changing a height of said cell-layout region so as to equalize an estimated value of virtual wire congestion degree in a horizontal wire within the cell-layout region on the same column, and determining again the cell-layout within the cell-layout region changed in height; and a ninth step for changing a width of said cell-layout region so as to equalize an estimated value of virtual wire congestion degree in a vertical wire within the cell-layout region on the same row, and determining again the cell-layout within the cell-layout region changed in width.
Claim 4
Dependent Claim
91 words
A method of a cell-layout in an integrated circuit device according to claim 1 , wherein in the third step, by use of logic hierarchy structure information added to the cells at the time of a logic design of the integrated circuit, defined as a cluster is a set of cells included in the largest logic hierarchy block among those smaller than an upper limit of a cluster size determined in response to the size of the small region generated by the division of the cell-layout region by said cut line.
Claim 5
Dependent Claim
65 words
A method of a cell-layout in an integrated circuit device according to claim 3 , wherein at the third step, set as a cluster is only a block such that a ratio of the number of signal lines connected with only the cells within the logic hierarchy block to the number of signal lines connected with said cells is larger than a predetermined reference value.
Claim 6
Dependent Claim
42 words
A method of a cell-layout in an integrated circuit device according to claim 1 , wherein the Min-Cut division with respect to the plurality of cut lines in the sixth step is implemented in independent, parallel process by a plurality of CPUs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-07 | 2006-04-08 | 2006-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-07 | 2010-04-08 | 2010-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-07 | 2014-04-08 | 2014-10-08 | $7700.00 | Window Closed / Lapsed |