US6460127B1
Expired / Lapsed
US
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Apparatus and method for signal processing
Assignee: GSI Technology Israel Ltd
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Filing: 1998-10-26
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Granted: 2002-10-01
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Expires: 2018-10-26
Abstract
Abstract An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare operation and the I/O buffer register memory cells perform at least one write operation.
Inventors
- 👤 Avidan Akerib
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:46
CPC Classifications
G; G06; G06T; G06T7/00; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023; G06F15/8038; G06V; G06V10/00; G06V10/40; G06V10/44; G06V10/443; G06V10/94; G06V10/955
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
104 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: a two-dimensional array of processors, each said processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of said processors; and a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors, said at least one register providing communication between processors which are processing non-adjacent samples; wherein the register array is operative to perform at least one multicell shift operation.
Claim 2
Dependent Claim
104 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: a two-dimensional array of processors, each said processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of said processors; and a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors, said at least one register providing communication between processors which are processing non-adjacent samples; wherein the register array is operative to perform at least one multicell shift operation.
Claim 3
Dependent Claim
12 words
Apparatus according to claim 1 which is operative in video real time.
Claim 4
Dependent Claim
11 words
Apparatus according to claim 1 wherein the signal comprises an image.
Claim 5
Dependent Claim
12 words
Apparatus according to claim 3 wherein the image comprises a color image.
Claim 6
Dependent Claim
19 words
Apparatus according to claim 1 wherein at least one sample is processed by two or more of the processors.
Claim 7
Dependent Claim
17 words
Apparatus according to claim 1 wherein at least one of the processors processes more than one sample.
Claim 8
Dependent Claim
14 words
Apparatus according to claim 1 wherein the register array comprises a plurality of registers.
Claim 9
Dependent Claim
22 words
Apparatus according to claim 1 wherein the register array includes a plurality of registers operative to store responders arriving from the processors.
Claim 10
Dependent Claim
19 words
Apparatus according to claim 1 and also comprising all I/O buffer register operative to input and output a signal.
Claim 11
Dependent Claim
23 words
Apparatus according to claim 9 wherein the processor array, the register array and the I/O buffer register are arranged on a single module.
Claim 12
Dependent Claim
24 words
Apparatus according to claim 9 wherein the processor array, the register array and the I/O buffer register are arranged on a single silicon die.
Claim 13
Dependent Claim
33 words
Apparatus according to claim 11 wherein the I/O buffer register includes a plurality of buffer register cells whose number is at least equal to the number of processors in said two-dimensional processor array.
Claim 14
Dependent Claim
109 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs an image differs from the row/column order of the image and wherein the register array is operative to perform at least one multicell shift operation.
Claim 15
Dependent Claim
109 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs an image differs from the row/column order of the image and wherein the register array is operative to perform at least one multicell shift operation.
Claim 16
Dependent Claim
24 words
Apparatus according to claim 13 , wherein the processor array, the register array and the I/O buffer register are arranged on a single chip.
Claim 17
Dependent Claim
18 words
Apparatus according to claim 13 , wherein said I/O buffer register and said processors are operative in parallel.
Claim 18
Dependent Claim
26 words
Apparatus according to claim 13 , wherein the word length of the I/O buffer register is increasable by decreasing the wordlength of the associative memory cells.
Claim 19
Dependent Claim
12 words
Apparatus according to claim 13 which is operative in video real time.
Claim 20
Dependent Claim
11 words
Apparatus according to claim 13 wherein the signal comprises an image.
Claim 21
Dependent Claim
12 words
Apparatus according to claim 18 wherein the image comprises a color image.
Claim 22
Dependent Claim
112 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs the samples differs from the order of the samples within the incoming signal and wherein the register array is operative to perform at least one multicell shift operation.
Claim 23
Dependent Claim
112 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs the samples differs from the order of the samples within the incoming signal and wherein the register array is operative to perform at least one multicell shift operation.
Claim 24
Dependent Claim
24 words
Apparatus according to claim 20 , wherein the processor array, the register array and the I/O buffer register are arranged on a single chip.
Claim 25
Dependent Claim
18 words
Apparatus according to claim 20 , wherein said I/O buffer register and said processors are operative in parallel.
Claim 26
Dependent Claim
26 words
Apparatus according to claim 20 , wherein the word length of the I/O buffer register is increasable by decreasing the wordlength of the associative memory cells.
Claim 27
Dependent Claim
12 words
Apparatus according to claim 20 which is operative in video real time.
Claim 28
Dependent Claim
11 words
Apparatus according to claim 20 wherein the signal comprises an image.
Claim 29
Dependent Claim
12 words
Apparatus according to claim 25 wherein the image comprises a color image.
Claim 30
Dependent Claim
134 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of the processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; an I/O buffer register operative to input all incoming signal and to output an outgoing signal; and an image correction system whereby: (i) a multiplicity of pixels from a distorted image are provided to a respective multiplicity of said associative memory cells; (ii) a transformation for an output of said image to compensate for said distortion is provided; and (iii) said transformation is executed in parallel for a plurality of said pixels via said register array.
Claim 31
Dependent Claim
134 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of the processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; an I/O buffer register operative to input all incoming signal and to output an outgoing signal; and an image correction system whereby: (i) a multiplicity of pixels from a distorted image are provided to a respective multiplicity of said associative memory cells; (ii) a transformation for an output of said image to compensate for said distortion is provided; and (iii) said transformation is executed in parallel for a plurality of said pixels via said register array.
Claim 32
Dependent Claim
22 words
The associative signal procession apparatus of claim 27 , wherein said distorted image is provided by a High Definition Television (HDTV) lens.
Claim 33
Dependent Claim
133 words
Associative signal processing apparatus for processing, an incoming signal comprising a plurality of samples, the apparatus comprising: two-dimensional array of processors each processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors; a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors; and image correction system whereby: (i) a multiplicity of pixels from a distorted image are provided to a respective multiplicity of said content addressable memory cells; (ii) a transformation for an output of said image to compensate for said distortion is provided; and (iii) said transformation is executed in parallel for a plurality of said pixels via said register array.
Claim 34
Dependent Claim
133 words
Associative signal processing apparatus for processing, an incoming signal comprising a plurality of samples, the apparatus comprising: two-dimensional array of processors each processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors; a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors; and image correction system whereby: (i) a multiplicity of pixels from a distorted image are provided to a respective multiplicity of said content addressable memory cells; (ii) a transformation for an output of said image to compensate for said distortion is provided; and (iii) said transformation is executed in parallel for a plurality of said pixels via said register array.
Claim 35
Dependent Claim
22 words
The associative signal processing apparatus of claim 29 , wherein said distorted image is provided by a High Definition Television (HDTV) lens.
Claim 36
Dependent Claim
148 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: a two-dimensional array of processors, each said processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of said processors; a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors, said at least one register providing communication between processors which are processing non-adjacent samples; and an I/O buffer register operative to input and output a signal; wherein the processor array, the register array and the I/O buffer register are arranged on a single silicon die and wherein the I/O buffer register includes a plurality of buffer register cells whose number is at least equal to the number of processors in said two-dimensional array.
Claim 37
Dependent Claim
148 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: a two-dimensional array of processors, each said processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of said processors; a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors, said at least one register providing communication between processors which are processing non-adjacent samples; and an I/O buffer register operative to input and output a signal; wherein the processor array, the register array and the I/O buffer register are arranged on a single silicon die and wherein the I/O buffer register includes a plurality of buffer register cells whose number is at least equal to the number of processors in said two-dimensional array.
Claim 38
Dependent Claim
116 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs an image differs from the row/column order of the image and wherein the word length of the I/O buffer register is increasable by decreasing the word length of the associative memory cells.
Claim 39
Dependent Claim
116 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs an image differs from the row/column order of the image and wherein the word length of the I/O buffer register is increasable by decreasing the word length of the associative memory cells.
Claim 40
Dependent Claim
119 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs the samples differs from the order of the samples within the incoming signal and wherein the word length of the I/O buffer register is increasable by decreasing the word length of the associative memory cells.
Claim 41
Dependent Claim
119 words
Associative signal processing apparatus comprising: an array of processors, each processor including a multiplicity of associative memory cells, at least one of said processors being operative to process a plurality of samples of an incoming signal; a register array including at least one register operative to store responders arriving from the processors and to provide communication between processors; and an I/O buffer register operative to input an incoming signal and to output an outgoing signal; wherein the order in which the I/O buffer inputs the samples differs from the order of the samples within the incoming signal and wherein the word length of the I/O buffer register is increasable by decreasing the word length of the associative memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-30 | 2006-04-01 | 2006-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-30 | 2010-04-01 | 2010-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-30 | 2014-04-01 | 2014-10-01 | $7700.00 | Window Closed / Lapsed |