US6449762B1
Expired / Lapsed
US
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Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesis
Assignee: Synopsys Inc
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Filing: 1999-10-07
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Granted: 2002-09-10
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Expires: 2019-10-07
Abstract
Abstract A method and apparatus that maintains the correspondence between a text representation of a circuit element and the corresponding schematic representation of the element after optimization of the circuit containing the element. In one example of a method of the invention, a circuit containing element is described in text representation. A first tag is assigned to the text representation. The text representation is synthesized to produce a first schematic representation of the circuit element. A second tag corresponding to the first tag is assigned to the first schematic representation of the circuit element. The circuit containing the circuit element is optimized to produce a second schematic representation of the circuit element. A third tag corresponding to the first tag is assigned to the second schematic representation. Other methods and apparatuses are described.
Inventors
- 👤 Kenneth S. McElvain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:00
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
120 words
A method for designing logic circuits comprising; compiling a test representation of a logic circuit; optimizing said logic circuit; graphically displaying at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said text representation; constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit; assigning a first identifier tag to said text representation of said logic circuit, assigning a second identifier tag to said graphic representation of said logic circuit, said second identifier tag being linked to said first identifier tag; and displaying said portion of said graphic representation which corresponds to said portion of said text representation.
Claim 2
Independent Claim
120 words
A method for designing logic circuits comprising; compiling a test representation of a logic circuit; optimizing said logic circuit; graphically displaying at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said text representation; constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit; assigning a first identifier tag to said text representation of said logic circuit, assigning a second identifier tag to said graphic representation of said logic circuit, said second identifier tag being linked to said first identifier tag; and displaying said portion of said graphic representation which corresponds to said portion of said text representation.
Claim 3
Dependent Claim
42 words
The method of claim 1 wherein said text representation is written in a hardware description language and wherein said displaying of said portion of said graphic representation is after said optimizing and wherein said optimizing is for a target integrated circuit architecture.
Claim 4
Dependent Claim
36 words
The method of claim 2 further comprising assigning a third identifier tag to said circuit representation of said logic circuit after optimizing said logic circuit, said third identifier tag being linked to said first identifier tag.
Claim 5
Independent Claim
134 words
A method for designing logic circuits comprising: describing a first circuit in text representation; assigning a first identifier tag to at least a portion of said text representation; synthesizing said text representation to produce a first schematic representation of said first circuit; assigning a second tag corresponding to said first tag to at least a portion of said first schematic representation of said first circuit; optimizing, through a Boolean relationship, said first circuit to produce a second schematic representation of said first circuit; constructing a correlation between at least said portion of said text representation and said second schematic representation after optimizing said first circuit; and assigning a third tag corresponding to said first tag to at least a portion of said second schematic representation, said third tag being linked to said first tag.
Claim 6
Independent Claim
134 words
A method for designing logic circuits comprising: describing a first circuit in text representation; assigning a first identifier tag to at least a portion of said text representation; synthesizing said text representation to produce a first schematic representation of said first circuit; assigning a second tag corresponding to said first tag to at least a portion of said first schematic representation of said first circuit; optimizing, through a Boolean relationship, said first circuit to produce a second schematic representation of said first circuit; constructing a correlation between at least said portion of said text representation and said second schematic representation after optimizing said first circuit; and assigning a third tag corresponding to said first tag to at least a portion of said second schematic representation, said third tag being linked to said first tag.
Claim 7
Dependent Claim
16 words
The method of claim 4 wherein said text representation is written in a hardware description language.
Claim 8
Dependent Claim
21 words
The method of claim 5 wherein said first schematic representation and said second schematic representation comprise register transfer level netlist objects.
Claim 9
Dependent Claim
37 words
The method of claim 6 further comprising: displaying said second schematic representation; displaying said text representation; and displaying in highlight a portion of said text representation and displaying in highlight a portion of said second schematic representation.
Claim 10
Dependent Claim
145 words
A computer readable medium having stored thereon sequences of instruction which are executable by a digital processing system, and which, when executed by the digital processing system, cause the system to preform a method comprising: compiling a text representation of a logic circuit; optimizing said logic circuit; graphically displaying at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said text representation; constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said graphic representation, said second identifier tag being linked to said first identifier tag; and displaying said portion of said graphic representation which corresponds to said portion of said representation.
Claim 11
Dependent Claim
145 words
A computer readable medium having stored thereon sequences of instruction which are executable by a digital processing system, and which, when executed by the digital processing system, cause the system to preform a method comprising: compiling a text representation of a logic circuit; optimizing said logic circuit; graphically displaying at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said text representation; constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said graphic representation, said second identifier tag being linked to said first identifier tag; and displaying said portion of said graphic representation which corresponds to said portion of said representation.
Claim 12
Dependent Claim
45 words
A computer readable medium as in claim 8 wherein said text representation is written in a hardware description language and wherein said displaying of said portion of said graphic representation is after said optimizing and wherein said optimizing is for a target integrated circuit architecture.
Claim 13
Dependent Claim
43 words
A computer readable medium as in claim 8 wherein said correlation links said second identifier tag to said first identifier tag and wherein said selecting is performed by a user manipulating a cursor control device to select said portion of said text representation.
Claim 14
Dependent Claim
39 words
A computer readable medium as in claim 10 wherein said selecting produces a display of highlighted text, and wherein said displaying of said portion of said graphic representation displays said portion of said graphic representation in a highlighted format.
Claim 15
Dependent Claim
155 words
A computer system comprising: a bus; a data storage device coupled to said bus; and a processor coupled to said data storage device, said processor operable to receive instruction which, when executed by the processor, cause the processor to perform a method comprising: complining a text representation of a logic circuit; optimizing said logic circuit for a target integrated circuit architecture; graphically displaying a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said text representation; constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said graphic representation, said second identifier tag being linked to said first identifier tag, and displaying said portion of said graphic representation which corresponds to said portion of said text representation.
Claim 16
Dependent Claim
155 words
A computer system comprising: a bus; a data storage device coupled to said bus; and a processor coupled to said data storage device, said processor operable to receive instruction which, when executed by the processor, cause the processor to perform a method comprising: complining a text representation of a logic circuit; optimizing said logic circuit for a target integrated circuit architecture; graphically displaying a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said text representation; constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said graphic representation, said second identifier tag being linked to said first identifier tag, and displaying said portion of said graphic representation which corresponds to said portion of said text representation.
Claim 17
Dependent Claim
33 words
A computer system as in claim 12 wherein said text representation is written in a hardware description language and wherein said displaying of said portion of said graphic representation is after said optimizing.
Claim 18
Dependent Claim
42 words
A computer system as in claim 12 wherein said correlation links said second identifier tag to said first identifier tag and wherein said selecting is performed by a user manipulating a cursor control device to select said portion of said text representation.
Claim 19
Dependent Claim
38 words
A computer system as in claim 14 wherein said selecting produces a display of highlighted text, and wherein said displaying of said portion of said graphic representation displays said portion of said graphic representation in a highlighted format.
Claim 20
Independent Claim
130 words
A method for designing logic circuits, said method comprising: compiling a text representation of a logic circuit; optimizing said logic circuit through a Boolean relationship; graphically displaying a graphical schematic of at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said graphical schematic; constructing a correlation between said portion of said text representation and said portion of said graphical schematic after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said text graphical schematic, said second identifier tag being linked to said first identifier tag; and displaying a portion of said text representation which corresponds to said portion of said graphical schematic.
Claim 21
Independent Claim
130 words
A method for designing logic circuits, said method comprising: compiling a text representation of a logic circuit; optimizing said logic circuit through a Boolean relationship; graphically displaying a graphical schematic of at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said graphical schematic; constructing a correlation between said portion of said text representation and said portion of said graphical schematic after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said text graphical schematic, said second identifier tag being linked to said first identifier tag; and displaying a portion of said text representation which corresponds to said portion of said graphical schematic.
Claim 22
Dependent Claim
61 words
A method as in claim 16 wherein said selecting of said portion of said graphical schematic results in said portion being displayed in a first highlighted manner relative to a remainder of said graphical schematic and wherein said portion of said text representation is displayed in a second highlighted manner relative to a remainder of said text representation which is displayed.
Claim 23
Dependent Claim
17 words
A method as in claim 17 wherein said text representation is written in a hardware description language.
Claim 24
Dependent Claim
41 words
A method as in claim 16 wherein said correlation links said second identifier tag to said first identifier tag and wherein said selecting is performed by a user manipulating a cursor control device to select said portion of said graphical schematic.
Claim 25
Dependent Claim
148 words
A computer readable medium having stored thereon a sequence of executable instructions which, when executed on a digital processing system, cause said system to preform a method comprising: compiling a text representation of a logic circuit; optimizing said logic circuit through a Boolean relationship; graphically displaying a graphical schematic of at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said graphical schematic; constructing a correlation between said portion of said text representation and said portion of said graphical schematic after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said graphical schematic, said second identifier tag being linked to said first identifier tag; and displaying a portion of said text representation which corresponds to said portion of said graphical schematic.
Claim 26
Dependent Claim
148 words
A computer readable medium having stored thereon a sequence of executable instructions which, when executed on a digital processing system, cause said system to preform a method comprising: compiling a text representation of a logic circuit; optimizing said logic circuit through a Boolean relationship; graphically displaying a graphical schematic of at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit; selecting a portion of said graphical schematic; constructing a correlation between said portion of said text representation and said portion of said graphical schematic after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said portion of said graphical schematic, said second identifier tag being linked to said first identifier tag; and displaying a portion of said text representation which corresponds to said portion of said graphical schematic.
Claim 27
Dependent Claim
63 words
A computer readable medium as in claim 20 wherein said selecting of said portion of said graphical schematic results in said portion being displayed in a first highlighted manner relative to a remainder of said graphical schematic and wherein said portion of said text representation is displayed in a second highlighted manner relative to a remainder of said text representation which is displayed.
Claim 28
Dependent Claim
19 words
A computer readable medium as in claim 21 wherein said text representation is written in a hardware description language.
Claim 29
Dependent Claim
43 words
A computer readable medium as in claim 20 wherein said correlation links said second identifier tag to said first identifier tag and wherein said selecting is performed by a user manipulating a cursor control device to select said portion of said graphical schematic.
Claim 30
Independent Claim
119 words
A method for designing logic circuits, said method comprising: displaying at least a portion of a text representation of a logic circuit; selecting a first portion of said at least a portion of said text representation; constructing a correlation between at least said portion of said text representation and a portion of graphical schematic after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said graphical schematic, said second identifier tag being linked tag said first identifier tag; displaying, in response to said selecting, a first portion of said graphical schematic which had been derived from said text representation and them optimized through a Boolean relationship.
Claim 31
Independent Claim
119 words
A method for designing logic circuits, said method comprising: displaying at least a portion of a text representation of a logic circuit; selecting a first portion of said at least a portion of said text representation; constructing a correlation between at least said portion of said text representation and a portion of graphical schematic after optimizing said logic circuit; assigning a first identifier tag to said portion of said text representation; assigning a second identifier tag to said graphical schematic, said second identifier tag being linked tag said first identifier tag; displaying, in response to said selecting, a first portion of said graphical schematic which had been derived from said text representation and them optimized through a Boolean relationship.
Claim 32
Independent Claim
124 words
A method for designing logic circuits, said method comprising: displaying at least a portion of a graphical schematic of a logic circuit, said graphical schematic having been derived from a text representation of said logic circuit and the optimized through a Boolean relationship; selecting a first portion of said graphical schematic; constructing a correlation between said portion of said graphical schematic and said text representation after optimizing said logic circuit; assigning a first identifier tag to said portion of said graphical schematic; assigning a second identifier tag to said text representation, said second identifier tag being linked to said first identifier tag; displaying, in response to said selecting, a portion of said representation from which said first portion of said graphical schematic was derived.
Claim 33
Independent Claim
124 words
A method for designing logic circuits, said method comprising: displaying at least a portion of a graphical schematic of a logic circuit, said graphical schematic having been derived from a text representation of said logic circuit and the optimized through a Boolean relationship; selecting a first portion of said graphical schematic; constructing a correlation between said portion of said graphical schematic and said text representation after optimizing said logic circuit; assigning a first identifier tag to said portion of said graphical schematic; assigning a second identifier tag to said text representation, said second identifier tag being linked to said first identifier tag; displaying, in response to said selecting, a portion of said representation from which said first portion of said graphical schematic was derived.
Claim 34
Dependent Claim
30 words
A method as in claim 25 , said method further comprising: selecting for display a portion of said graphical schematic which is in a critical path of said logic circuit.
Claim 35
Dependent Claim
34 words
A method as in claim 26 wherein said selecting specifies a particular type of logic gate for display such that a filtered graphical schematic of only said particular type of logic gates is displayed.
Claim 36
Dependent Claim
23 words
A method as in claim 26 wherein said selecting is performed by a user manipulating a cursor control device to select said portion.
Claim 37
Dependent Claim
148 words
A computer readable medium having stored thereon executable computer program instructions which, when executed by a digital processing system, cause said system to perform a method for designing logic circuits, said method comprising: generating a first representation of a logic circuit; performing an optimization of said logic circuit to create a second representation which represents a transformation of said first representation, said optimization being performed through a Boolean relationship; assigning a first identifier tag to said first representation; assigning a second identifier tag to said second representation, said second identifier tag being linked to said first identifier tag; and correlating a first set of intermediate nodes in said first representation to a second set of intermediate nodes in said second representation, wherein said correlating creates a set of matched tags for said first and said sescond sets of intermediate nodes after performing said optimization of said logic circuit.
Claim 38
Dependent Claim
148 words
A computer readable medium having stored thereon executable computer program instructions which, when executed by a digital processing system, cause said system to perform a method for designing logic circuits, said method comprising: generating a first representation of a logic circuit; performing an optimization of said logic circuit to create a second representation which represents a transformation of said first representation, said optimization being performed through a Boolean relationship; assigning a first identifier tag to said first representation; assigning a second identifier tag to said second representation, said second identifier tag being linked to said first identifier tag; and correlating a first set of intermediate nodes in said first representation to a second set of intermediate nodes in said second representation, wherein said correlating creates a set of matched tags for said first and said sescond sets of intermediate nodes after performing said optimization of said logic circuit.
Claim 39
Dependent Claim
20 words
A computer readable medium as in claim 29 wherein said first representation is an RTL netlist or a schematic representation.
Claim 40
Dependent Claim
20 words
A computer readable medium as in claim 29 wherein said second representation is an RTL netlist or a schematic representation.
References Cited (Backward Citations)
US5555201A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-09 | 2006-03-11 | 2006-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-09 | 2010-03-11 | 2010-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-09 | 2014-03-11 | 2014-09-10 | $7700.00 | Window Closed / Lapsed |