US6396341B1
Expired / Lapsed
US
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Class E Doherty amplifier topology for high efficiency signal transmitters
Assignee: Ericsson Inc
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Filing: 2000-12-29
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Granted: 2002-05-28
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Expires: 2020-12-29
Abstract
Abstract A Doherty amplifier circuit is provided comprising a digital signal processor for producing separated amplitude and phase modulated waveforms, and a plurality of class E amplifiers in communication with the digital signal processor. Each of the amplifiers has an input for receiving signals corresponding to the waveforms, and outputs linked to a shared load network. In this way, a scheme for efficient amplification of amplitude modulated waveforms is achieved across a wide dynamic range and for a large peak-to-average ratio using only input modulated techniques.
Inventors
- 👤 David R. Pehlke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:26
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/217; H03F3/2176; H03F1/00; H03F1/02; H03F1/04; H03F1/06; H03F1/07; H03F1/0205; H03F1/0288
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
52 words
An amplifier circuit comprising: a digital signal processor for producing separated amplitude and phase modulated waveforms; and a plurality of class E amplifiers in communication with said digital signal processor, each of said amplifiers having an input for receiving signals corresponding to said waveforms, and outputs linked to a shared load network.
Claim 2
Dependent Claim
52 words
An amplifier circuit comprising: a digital signal processor for producing separated amplitude and phase modulated waveforms; and a plurality of class E amplifiers in communication with said digital signal processor, each of said amplifiers having an input for receiving signals corresponding to said waveforms, and outputs linked to a shared load network.
Claim 3
Dependent Claim
27 words
The amplifier circuit of claim 1 wherein said circuit is configured to allow one of said amplifiers to saturate prior to saturation of others of said amplifiers.
Claim 4
Dependent Claim
18 words
The amplifier circuit of claim 1 wherein at least two of said amplifiers have different output power ratings.
Claim 5
Dependent Claim
54 words
The amplifier circuit of claim 1 wherein said plurality of class E amplifiers further comprises a first and a second amplifier, said first amplifier functioning as a carrier amplifier receiving a first amplitude-modulated baseband signal from said digital signal processor, said second amplifier receiving a second amplitude-modulated baseband signal from said digital signal processor.
Claim 6
Dependent Claim
27 words
The amplifier circuit of claim 1 wherein each of said class E amplifiers is configured to utilize an envelope signal to adjust its individual output power level.
Claim 7
Dependent Claim
37 words
The amplifier circuit of claim 2 further comprising a plurality of digital to analog converters in communication with said digital signal processor, said converters for converting said signals to high-resolution analog signals for input to said amplifiers.
Claim 8
Dependent Claim
23 words
The amplifier circuit of claim 2 further comprising at least one modulating upconverter linked to said digital signal processor for modulating said waveforms.
Claim 9
Dependent Claim
18 words
The amplifier circuit of claim 5 further comprising at least one bandpass noise filter linked to said upconverter.
Claim 10
Dependent Claim
17 words
The amplifier circuit of claim 6 further comprising an impedance adjusting element linked to said peaking amplifier.
Claim 11
Dependent Claim
85 words
The circuit of claim 5 further comprising: a control device for at least one of said amplifiers for receiving amplitude information or phase information from a primary waveform, and a plurality of switching devices in communication with said control device and said at least one amplifier, said switching devices each having a different current resistance; wherein said control device uses said information to select an active switching device to create a secondary waveform for input to the matching network of said at least one amplifier.
Claim 12
Dependent Claim
34 words
The circuit of claim 10 wherein said switching devices are transistors each having a gate, and said control device controls said switching devices by providing said information at the gate of said switching device.
Claim 13
Dependent Claim
48 words
The circuit of claim 1 further comprising: a feedback loop for sensing VSWR reflection from an antenna in communication with one of said amplifiers, said feedback loop in communication with said digital signal processor; wherein said digital signal processor adjusts said waveforms to correct for said VSWR reflection.
Claim 14
Dependent Claim
138 words
An amplifier circuit comprising: a digital signal processor producing a plurality of digital amplitude modulation signals and at least one digital phase modulated signal; a plurality of digital to analog converters in communication with said digital signal processor for converting said digital amplitude modulation signals into analog amplitude modulation signals, and for converting said digital phase modulated signal into an analog phase modulated signal; a plurality of class E amplifiers in communication with said digital to analog converters to receive said analog signals, at least one of said amplifiers functioning as a carrier amplifier connected to receive said analog phase modulated signal and one of said analog amplitude modulation signals, and at least another of said amplifiers functioning as a peaking amplifier connected to receive said analog phase modulated signal and another of said analog amplitude modulation signals.
Claim 15
Dependent Claim
138 words
An amplifier circuit comprising: a digital signal processor producing a plurality of digital amplitude modulation signals and at least one digital phase modulated signal; a plurality of digital to analog converters in communication with said digital signal processor for converting said digital amplitude modulation signals into analog amplitude modulation signals, and for converting said digital phase modulated signal into an analog phase modulated signal; a plurality of class E amplifiers in communication with said digital to analog converters to receive said analog signals, at least one of said amplifiers functioning as a carrier amplifier connected to receive said analog phase modulated signal and one of said analog amplitude modulation signals, and at least another of said amplifiers functioning as a peaking amplifier connected to receive said analog phase modulated signal and another of said analog amplitude modulation signals.
Claim 16
Dependent Claim
24 words
The amplifier circuit of claim 12 further comprising at least one modulating upconverter linked to said digital signal processor for modulating said RF signal.
Claim 17
Dependent Claim
18 words
The amplifier circuit of claim 14 further comprising at least one bandpass noise filter linked to said upconverter.
Claim 18
Dependent Claim
16 words
The amplifier circuit of claim 13 further comprising an impedance adjusting element linked to said amplifiers.
Claim 19
Dependent Claim
27 words
The circuit of claim 13 , wherein said class E amplifiers each include envelope adjustment circuitry to adjust the power level for each amplifier in said circuit.
Claim 20
Dependent Claim
18 words
The amplifier circuit of claim 13 wherein at least two of said amplifiers have different output power ratings.
Claim 21
Dependent Claim
33 words
The circuit of claim 13 , wherein said converters are capable of processing at a high bit rate to output high-resolution analog signals corresponding to the signals received from the digital signal processor.
Claim 22
Dependent Claim
52 words
The circuit of claim 13 , wherein said digital signal processor includes: two amplitude-modulated outputs linked via separate digital to analog converters to each of two of said amplifiers; and a quadrature modulating upconverter and a bandpass filter in series communication with each of said phase-modulated outputs of said digital signal processor.
Claim 23
Dependent Claim
19 words
The circuit of claim 13 further comprising means for modulating the input to at least one of said amplifiers.
Claim 24
Dependent Claim
48 words
The circuit of claim 13 further comprising: a feedback loop for sensing VSWR reflection from an antenna in communication with one of said amplifiers, said feedback loop in communication with said digital signal processor; wherein said digital signal processor adjusts said waveforms to correct for said VSWR reflection.
Claim 25
Independent Claim
125 words
A method of providing high-efficiency and high peak-to-average signal amplification, said method comprising the steps of: providing first and second digital amplitude waveforms from a digital signal processor; providing a first digital phase waveform from said digital signal processor; converting said first digital amplitude waveform into a first analog amplitude waveform, and said second digital amplitude waveform into a second analog amplitude waveform; converting said first digital phase waveform into a first analog phase waveform; generating a first output signal with a carder amplifier from said first analog amplitude waveform and said first analog phase waveform; generating a second output signal with a peaking amplifier from said second analog amplitude waveform and said second analog phase waveform; and combining said first and second output signals.
Claim 26
Independent Claim
125 words
A method of providing high-efficiency and high peak-to-average signal amplification, said method comprising the steps of: providing first and second digital amplitude waveforms from a digital signal processor; providing a first digital phase waveform from said digital signal processor; converting said first digital amplitude waveform into a first analog amplitude waveform, and said second digital amplitude waveform into a second analog amplitude waveform; converting said first digital phase waveform into a first analog phase waveform; generating a first output signal with a carder amplifier from said first analog amplitude waveform and said first analog phase waveform; generating a second output signal with a peaking amplifier from said second analog amplitude waveform and said second analog phase waveform; and combining said first and second output signals.
Claim 27
Dependent Claim
40 words
The method of claim 23 further comprising the steps of: sensing VSWR reflection from an antenna in communication with one of said amplifiers; and adjusting said digital amplitude and phase waveforms within said processor to correct for said VSWR reflection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-05-27 | 2005-11-26 | 2006-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-27 | 2009-11-26 | 2010-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-27 | 2013-11-26 | 2014-05-28 | $7700.00 | Window Closed / Lapsed |