US6366154B2
Expired / Lapsed
US
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Method and circuit to perform a trimming phase
Assignee: STMicroelectronics SRL
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Filing: 2001-01-26
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Granted: 2002-04-02
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Expires: 2021-01-26
Abstract
Abstract A method is provided for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin. According to the method, a single pin is enabled to receive trimming data by biasing the pin to outside its operating range. A clock signal is obtained from a division of the bias potential of the pin, and the logic value of the trimming data is obtained from a different division of the bias potential of the pin. Serial acquisition of the data is enabled in accordance with the clock signal, and the data is transferred to the modification circuit.
Inventors
- 👤 Francesco Pulvirenti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:02
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
124 words
A method for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin, said method comprising the steps of: enabling a single pin to receive trimming data by biasing the pin to outside its operating range; obtaining a clock signal from a division of the bias potential of the pin; obtaining the logic value of the trimming data from a different division of the bias potential of the pin; enabling serial acquisition of the data in accordance with the clock signal; transferring the data to the modification circuit.
Claim 2
Independent Claim
124 words
A method for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin, said method comprising the steps of: enabling a single pin to receive trimming data by biasing the pin to outside its operating range; obtaining a clock signal from a division of the bias potential of the pin; obtaining the logic value of the trimming data from a different division of the bias potential of the pin; enabling serial acquisition of the data in accordance with the clock signal; transferring the data to the modification circuit.
Claim 3
Dependent Claim
31 words
The method according to claim 1 , further comprising the step of transferring the data to selection logic with the modification circuit bypassed on the occurrence of a simulated trimming operation.
Claim 4
Dependent Claim
18 words
The method according to claim 1 , wherein the transfer operation is earned out using a shift register.
Claim 5
Dependent Claim
29 words
The method according to claim 3 , further comprising the step of supplying the shift register with the data on one input and the clock signal on another input.
Claim 6
Dependent Claim
33 words
The method according to claim 1 , wherein the step of obtaining a clock signal includes the sub-step of comparing a division of the bias potential on the pin with a reference potential.
Claim 7
Dependent Claim
37 words
The method according to claim 1 , wherein the step of obtaining the logic value of the trimming data includes the sub-step of comparing a division of the bias potential on the pin with a reference potential.
Claim 8
Dependent Claim
82 words
The method according to claim 1 , wherein the step of obtaining a clock signal includes the sub-step of comparing a division of the bias potential on the pin with a reference potential, the step of obtaining the logic value of the trimming data includes the sub-step of comparing a division of the bias potential on the pin with a reference potential, and the trimming data logic value comparison threshold is higher than the comparison threshold used to obtain the clock signal.
Claim 9
Dependent Claim
82 words
An electronic circuit for carrying out a trimming operation on circuit portions of an integrated circuit having at least a first input or supply pin, an output pin, and a second supply pin, the circuit comprising: memory elements; means for modifying the state of the memory elements; and first and second comparators having their inputs connected to a trimming pin to produce a clock signal for the trimming operation and a sequence of trimming data, wherein a single trimming pin is used.
Claim 10
Dependent Claim
82 words
An electronic circuit for carrying out a trimming operation on circuit portions of an integrated circuit having at least a first input or supply pin, an output pin, and a second supply pin, the circuit comprising: memory elements; means for modifying the state of the memory elements; and first and second comparators having their inputs connected to a trimming pin to produce a clock signal for the trimming operation and a sequence of trimming data, wherein a single trimming pin is used.
Claim 11
Dependent Claim
43 words
The circuit according to claim 8 , wherein the first comparator has an input coupled to the trimming pin via a voltage divider, and the second comparator has an input coupled to the trimming pin via a different node of the voltage divider.
Claim 12
Dependent Claim
20 words
The circuit according to claim 9 , further comprising a shift register connected downstream of the first and second comparators.
Claim 13
Dependent Claim
16 words
The circuit according to claim 10 , wherein the shift register is of the n+2 order.
Claim 14
Dependent Claim
19 words
The circuit according to claim 10 , wherein the means of modifying is connected downstream of the shift register.
Claim 15
Dependent Claim
39 words
The circuit according to claim 10 , wherein the shift register receives trimming data on one input from the output of the second comparator, and receives a clock signal on another input from the output of the first comparator.
Claim 16
Dependent Claim
36 words
The circuit according to claim 10 , wherein the shift register has its output connected to selection logic so as to bypass the means of modifying on the occurrence of a simulation of the trimming results.
Claim 17
Dependent Claim
23 words
The circuit according to claim 14 , further comprising a multiplexer coupled between the outputs of the shift register and the selection logic.
Claim 18
Dependent Claim
29 words
The circuit according to claim 15 , wherein an n-th output of the shift register is connected to an input of the multiplexer to select a simulated trimming operation.
Claim 19
Dependent Claim
32 words
The circuit according to claim 14 , wherein the selection logic has its output connected to a voltage reference of the circuit portion producing a reference voltage signal for the integrated circuit.
Claim 20
Dependent Claim
24 words
The circuit according to claim 14 , wherein the memory elements are coupled between the outputs of the shift register and the selection logic.
Claim 21
Dependent Claim
24 words
The circuit according to claim 15 , wherein the memory elements arc coupled between the outputs of the shift register and the selection logic.
Claim 22
Dependent Claim
89 words
An information processing system including at least one electronic circuit for carrying out a trimming operation on circuit portions of an integrated circuit having at least a first input or supply pin, an output pin, and a second supply pin, the circuit comprising: memory elements; means for modifying the state of the memory elements; and first and second comparators having their inputs connected to a trimming pin to produce a clock signal for the trimming operation and a sequence of trimming data, wherein a single trimming pin is used.
Claim 23
Dependent Claim
89 words
An information processing system including at least one electronic circuit for carrying out a trimming operation on circuit portions of an integrated circuit having at least a first input or supply pin, an output pin, and a second supply pin, the circuit comprising: memory elements; means for modifying the state of the memory elements; and first and second comparators having their inputs connected to a trimming pin to produce a clock signal for the trimming operation and a sequence of trimming data, wherein a single trimming pin is used.
Claim 24
Dependent Claim
45 words
The information processing system according to claim 20 , wherein the first comparator has an input coupled to the trimming pin via a voltage divider, and the second comparator has an input coupled to the trimming pin via a different node of the voltage divider.
Claim 25
Dependent Claim
22 words
The information processing system according to claim 21 , further comprising a shift register connected downstream of the first and second comparators.
Claim 26
Dependent Claim
43 words
The information processing system according to claim 20 , further comprising a shift register that receives trimming data on one input from the output of the second comparator, and receives a clock signal on another input from the output of the first comparator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-01 | 2005-10-01 | 2006-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-01 | 2009-10-01 | 2010-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-01 | 2013-10-01 | 2014-04-02 | $7700.00 | Window Closed / Lapsed |