US6362045B1
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Method to form non-volatile memory cells
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 2000-05-09
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Granted: 2002-03-26
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Expires: 2020-05-09
Abstract
Abstract A new method of forming non-volatile memory cells with an improved bottom silicon dioxide layer of the O—N—O has been achieved. A semiconductor substrate is provided. A tunneling dielectric layer is grown overlying the semiconductor substrate. A polysilicon layer is deposited overlying the tunneling dielectric layer. Nitrogen is implanted into the polysilicon layer to form a nitridized surface region. The polysilicon layer and the tunneling dielectric layer are then patterned to form floating gates. A bottom silicon dioxide layer is grown overlying the floating gates by thermal oxidation of the polysilicon layer. The nitridized surface region reduces the rate of thermal oxidation and creates a smooth surface. A silicon nitride layer is deposited overlying the bottom silicon dioxide layer. A top silicon dioxide layer is formed overlying the silicon nitride layer to complete the O—N—O stack. A conductive layer, that may comprise polysilicon, is deposited overlying the top silicon dioxide layer. The conductive layer, the top silicon dioxide layer, the silicon nitride layer, and the bottom silicon dioxide layer are patterned to form control gates and to complete the non-volatile memory cells.
Inventors
- 👤 Yung-Tao Lin
- 👤 Chwa Siow Lee
- 👤 Chiew Sin Ping
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
177 words
A method to form non-volatile memory cells in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; growing a tunneling oxide layer overlying said semiconductor substrate; depositing a polysilicon layer overlying said tunneling oxide layer; implanting nitrogen into said polysilicon layer to form a nitridized surface region; thereafter patterning said polysilicon layer and said tunneling oxide layer to form floating gates; growing a bottom silicon dioxide layer overlying said floating gates where said growing is by thermal oxidation of said polysilicon layer and wherein said nitridized surface region reduces the rate of said thermal oxidation and cause a smooth surface to be grown; depositing a silicon nitride layer overlying said bottom silicon dioxide layer; forming a top silicon dioxide layer overlying said silicon nitride layer; depositing a conductive layer overlying said top silicon dioxide layer; and patterning said conductive layer, said top silicon dioxide layer, said silicon nitride layer, and said bottom silicon dioxide layer to form control gates and to complete said non-volatile memory cells in the manufacture of the integrated circuit device.
Claim 2
Independent Claim
177 words
A method to form non-volatile memory cells in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; growing a tunneling oxide layer overlying said semiconductor substrate; depositing a polysilicon layer overlying said tunneling oxide layer; implanting nitrogen into said polysilicon layer to form a nitridized surface region; thereafter patterning said polysilicon layer and said tunneling oxide layer to form floating gates; growing a bottom silicon dioxide layer overlying said floating gates where said growing is by thermal oxidation of said polysilicon layer and wherein said nitridized surface region reduces the rate of said thermal oxidation and cause a smooth surface to be grown; depositing a silicon nitride layer overlying said bottom silicon dioxide layer; forming a top silicon dioxide layer overlying said silicon nitride layer; depositing a conductive layer overlying said top silicon dioxide layer; and patterning said conductive layer, said top silicon dioxide layer, said silicon nitride layer, and said bottom silicon dioxide layer to form control gates and to complete said non-volatile memory cells in the manufacture of the integrated circuit device.
Claim 3
Dependent Claim
23 words
The method according to claim 1 wherein said polysilicon layer is deposited to a thickness of between about 1,000 Angstroms and 1,500 Angstroms.
Claim 4
Dependent Claim
40 words
The method according to claim 1 wherein said step of implanting said nitrogen comprises an implantation dose of between about 1×10 14 atoms/cm 2 and 5×10 14 atoms/cm 2 and an energy of between about 5 KeV and 10 KeV.
Claim 5
Dependent Claim
39 words
The method according to claim 1 wherein said nitridized surface region is implanted to a concentration of between about 5×10 18 atoms/cm 3 and 2×10 20 atoms/cm 3 and a depth of between about 100 Angstroms and 300 Angstroms.
Claim 6
Dependent Claim
25 words
The method according to claim 1 wherein said bottom silicon dioxide layer is grown to a thickness of between about 80 Angstroms and 100 Angstroms.
Claim 7
Dependent Claim
32 words
The method according to claim 1 further comprising implanting ions into said polysilicon layer to reduce resistivity after said step of depositing said polysilicon layer and before said step of implanting nitrogen.
Claim 8
Dependent Claim
41 words
The method according to claim 6 wherein said step of implanting ions comprises phosphorous implanted with a dose of between about 1×10 15 atoms/cm 2 and 2×10 15 atoms/cm 2 and an energy of between about 10 KeV and 30 KeV.
Claim 9
Dependent Claim
24 words
The method according to claim 1 wherein said polysilicon layer is insitu doped to a resistivity of between about 100 ohm/square and 1,000 ohm/square.
Claim 10
Independent Claim
183 words
A method to form non-volatile memory cells in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; growing a tunneling oxide layer overlying said semiconductor substrate; depositing a first polysilicon layer overlying said tunneling oxide layer; implanting nitrogen into said first polysilicon layer to form a nitridized surface region; thereafter patterning said first polysilicon layer and said tunneling oxide layer to form floating gates; growing a bottom silicon dioxide layer overlying said floating gates where said growing is by thermal oxidation of said first polysilicon layer and wherein said nitridized surface region reduces the rate of said thermal oxidation and causes a smooth surface to be grown; depositing a silicon nitride layer overlying said bottom silicon dioxide layer; forming a top silicon dioxide layer overlying said silicon nitride layer; depositing a second polysilicon layer overlying said top silicon dioxide layer; and patterning said second polysilicon layer, said top silicon dioxide layer, said silicon nitride layer, and said bottom silicon dioxide layer to form control gates and to complete said non-volatile memory cells in the manufacture of the integrated circuit device.
Claim 11
Independent Claim
183 words
A method to form non-volatile memory cells in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; growing a tunneling oxide layer overlying said semiconductor substrate; depositing a first polysilicon layer overlying said tunneling oxide layer; implanting nitrogen into said first polysilicon layer to form a nitridized surface region; thereafter patterning said first polysilicon layer and said tunneling oxide layer to form floating gates; growing a bottom silicon dioxide layer overlying said floating gates where said growing is by thermal oxidation of said first polysilicon layer and wherein said nitridized surface region reduces the rate of said thermal oxidation and causes a smooth surface to be grown; depositing a silicon nitride layer overlying said bottom silicon dioxide layer; forming a top silicon dioxide layer overlying said silicon nitride layer; depositing a second polysilicon layer overlying said top silicon dioxide layer; and patterning said second polysilicon layer, said top silicon dioxide layer, said silicon nitride layer, and said bottom silicon dioxide layer to form control gates and to complete said non-volatile memory cells in the manufacture of the integrated circuit device.
Claim 12
Dependent Claim
24 words
The method according to claim 9 wherein said first polysilicon layer is deposited to a thickness of between about 1,000 Angstroms and 1,500 Angstroms.
Claim 13
Dependent Claim
40 words
The method according to claim 9 wherein said step of implanting said nitrogen comprises an implantation dose of between about 1×10 14 atoms/cm 2 and 5×10 14 atoms/cm 2 and an energy of between about 5 KeV and 10 KeV.
Claim 14
Dependent Claim
39 words
The method according to claim 9 wherein said nitridized surface region is implanted to a concentration of between about 5×10 18 atoms/cm 3 and 2×10 20 atoms/cm 3 and a depth of between about 100 Angstroms and 300 Angstroms.
Claim 15
Dependent Claim
25 words
The method according to claim 9 wherein said bottom silicon dioxide layer is grown to a thickness of between about 80 Angstroms and 100 Angstroms.
Claim 16
Dependent Claim
34 words
The method according to claim 9 further comprising implanting ions into said first polysilicon layer to reduce resistivity after said step of depositing said first polysilicon layer and before said step of implanting nitrogen.
Claim 17
Dependent Claim
43 words
The method according to claim 9 wherein said step of implanting ions comprises phosphorous implanted with a dose of between about 1×10 15 atoms /cm 2 and 2×10 15 atoms /cm 2 and an energy of between about 10 KeV and 30 KeV.
Claim 18
Independent Claim
204 words
A method to form non-volatile memory cells in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate containing source and drain junctions for planned non-volatile memory cells; growing a tunneling oxide layer overlying said semiconductor substrate; depositing a first polysilicon layer overlying said tunneling oxide layer; implanting ions into said first polysilicon layer to reduce resistivity; thereafter implanting nitrogen into said first polysilicon layer to form a nitridized surface region; thereafter patterning said first polysilicon layer and said tunneling oxide layer to form floating gates; growing a bottom silicon dioxide layer overlying said floating gates where said growing is by thermal oxidation of said first polysilicon layer and wherein said nitridized surface region reduces the rate of said thermal oxidation and cause a smooth surface to be grown; depositing a silicon nitride layer overlying said bottom silicon dioxide layer; growing a top silicon dioxide layer overlying said silicon nitride layer; depositing a second polysilicon layer overlying said top silicon dioxide layer; and patterning said second polysilicon layer, said top silicon dioxide layer, said silicon nitride layer, and said bottom silicon dioxide layer to form control gates and to complete said non-volatile memory cells in the manufacture of the integrated circuit device.
Claim 19
Independent Claim
204 words
A method to form non-volatile memory cells in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate containing source and drain junctions for planned non-volatile memory cells; growing a tunneling oxide layer overlying said semiconductor substrate; depositing a first polysilicon layer overlying said tunneling oxide layer; implanting ions into said first polysilicon layer to reduce resistivity; thereafter implanting nitrogen into said first polysilicon layer to form a nitridized surface region; thereafter patterning said first polysilicon layer and said tunneling oxide layer to form floating gates; growing a bottom silicon dioxide layer overlying said floating gates where said growing is by thermal oxidation of said first polysilicon layer and wherein said nitridized surface region reduces the rate of said thermal oxidation and cause a smooth surface to be grown; depositing a silicon nitride layer overlying said bottom silicon dioxide layer; growing a top silicon dioxide layer overlying said silicon nitride layer; depositing a second polysilicon layer overlying said top silicon dioxide layer; and patterning said second polysilicon layer, said top silicon dioxide layer, said silicon nitride layer, and said bottom silicon dioxide layer to form control gates and to complete said non-volatile memory cells in the manufacture of the integrated circuit device.
Claim 20
Dependent Claim
24 words
The method according to claim 16 wherein said first polysilicon layer is deposited to a thickness of between about 1,000 Angstroms and 1,500 Angstroms.
Claim 21
Dependent Claim
40 words
The method according to claim 16 wherein said step of implanting said nitrogen comprises an implantation dose of between about 1×10 14 atoms/cm 2 and 5×10 14 atoms/cm 2 and an energy of between about 5 KeV and 10 KeV.
Claim 22
Dependent Claim
39 words
The method according to claim 16 wherein said nitridized surface region is implanted to a concentration of between about 5×10 18 atoms/cm 3 and 2×10 20 atoms/cm 3 and a depth of between about 100 Angstroms and 300 Angstroms.
Claim 23
Dependent Claim
25 words
The method according to claim 16 wherein said bottom silicon dioxide layer is grown to a thickness of between about 80 Angstroms and 100 Angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-03-25 | 2005-09-24 | 2006-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-25 | 2009-09-24 | 2010-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-25 | 2013-09-24 | 2014-03-26 | $7700.00 | Window Closed / Lapsed |