US6349062B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selective erasure of a non-volatile memory cell of a flash memory device
Assignee: Cypress Semiconductor Corp
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Filing: 2000-10-11
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Granted: 2002-02-19
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Expires: 2020-10-11
Abstract
Abstract A method of selectively erasing a bit of an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that include a first non-volatile two bit memory cell that is connected in series with a second non-volatile memory cell. The method includes erasing a first bit of the first non-volatile two bit memory cell while not erasing a second bit of the first non-volatile memory cell.
Inventors
- 👤 Timothy J. Thurgate
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:56
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0475; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
74 words
A method of selectively erasing a bit of an individual memory cell of an array of non-volatile memory cells, the method comprising: providing an array of non-volatile memory cells that comprises a first non-volatile two bit memory cell that is connected in series with a second non-volatile memory cell; and erasing a first bit of said first non-volatile two bit memory cell while not erasing a second bit of said first non-volatile memory cell.
Claim 2
Independent Claim
74 words
A method of selectively erasing a bit of an individual memory cell of an array of non-volatile memory cells, the method comprising: providing an array of non-volatile memory cells that comprises a first non-volatile two bit memory cell that is connected in series with a second non-volatile memory cell; and erasing a first bit of said first non-volatile two bit memory cell while not erasing a second bit of said first non-volatile memory cell.
Claim 3
Dependent Claim
20 words
The method of claim 1 , comprising applying a positive bias to a source of said first non-volatile memory cell.
Claim 4
Dependent Claim
20 words
The method of claim 2 , comprising applying a positive voltage to a drain of said first non-volatile memory cell.
Claim 5
Dependent Claim
37 words
The method of claim 2 , wherein the second non-volatile memory cell is adjacent to said first bit and is simultaneously grounded when said positive bias is applied to said source of said first non-volatile memory cell.
Claim 6
Dependent Claim
37 words
The method of claim 3 , wherein the second non-volatile memory cell is adjacent to said first bit and is simultaneously grounded when said positive bias is applied to said source of said first non-volatile memory cell.
Claim 7
Dependent Claim
25 words
The method of claim 2 , comprising applying a non-positive voltage to gates of said first non-volatile memory cell and said second non-volatile memory cell.
Claim 8
Dependent Claim
25 words
The method of claim 3 , comprising applying a non-positive voltage to gates of said first non-volatile memory cell and said second non-volatile memory cell.
Claim 9
Dependent Claim
24 words
The method of claim 3 wherein said positive bias has a magnitude such that hot holes are generated in said first non-volatile memory cell.
Claim 10
Dependent Claim
48 words
The method of claim 8 , wherein said positive bias has a magnitude that accelerates electrons within said first non-volatile memory cell to generate said hot holes via impact ionization within said first non-volatile memory cell while not producing significant band-to-band currents with said first non-volatile memory cell.
Claim 11
Dependent Claim
43 words
The method of claim 2 , wherein the magnitude of said positive bias is such as to accelerate electrons toward a drain of said first non-volatile memory cell, and said electrons are not injected into a gate of said first non-volatile memory cell.
Claim 12
Dependent Claim
28 words
The method of claim 8 , wherein said hot holes are injected into a gate of said first non-volatile memory cell so as to erase said first bit.
Claim 13
Dependent Claim
45 words
The method of claim 1 , wherein said first non-volatile memory cell comprises: a substrate that comprises a first region and a second region with a channel therebetween; a gate above said channel; and a charge trapping region that contains a first amount of charge.
Claim 14
Dependent Claim
17 words
The method of claim 1 , wherein said first non-volatile memory cell comprises an EEPROM memory cell.
Claim 15
Dependent Claim
29 words
The method of claim 12 , wherein said first non-volatile memory cell comprises: a P-type substrate; a dielectric layer that lies between said channel and said charge trapping region.
Claim 16
Dependent Claim
20 words
The method of claim 14 , wherein said memory cell further comprises an electrical isolation layer located above said channel.
Claim 17
Dependent Claim
13 words
The method of claim 14 , wherein said dielectric layer comprises silicon dioxide.
Claim 18
Dependent Claim
14 words
The method of claim 14 , wherein said charge trapping layer comprises silicon nitride.
References Cited (Backward Citations)
US5471423A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-18 | 2005-08-20 | 2006-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-18 | 2009-08-20 | 2010-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-18 | 2013-08-20 | 2014-02-19 | $7700.00 | Window Closed / Lapsed |