Line scanning circuit for a dual-mode display

Claim 2

A row select circuit for a display device having rows of picture elements (pixels), the row select circuit comprising: a plurality of broadcast control signals; a plurality of stages connected in series, each stage being coupled to a respective one of the rows of pixels and being coupled to receive a select signal from the previous stage wherein the first stage is coupled to receive a select signal at the start of an image frame, wherein each stage includes: first gating circuitry, responsive to the select signal for generating a further select signal to select the respective row of pixels, which further select signal is applied to the next successive stage as the select signal; second gating circuitry responsive to the further select signal to apply at least selected ones of the plurality of broadcast control signals to the selected row of pixels.

Claim 3

A row select circuit according to claim 1 , wherein the pixels in the rows of pixels are subject to an autozero operation and a data load operation and the broadcast control signals include: a first control signal which causes the pixels in the selected row of pixels to perform the autozero operation and a second control signal occurring after the first control signal, which causes the selected pixels to perform the data load operation.

Claim 4

A row select circuit according to claim 2 , wherein the pixels in the rows of pixels are further subject to a reset operation, occurring before the autozero operation and wherein the first gating circuitry applies control signals to the selected row of pixels to reset the selected row of pixels while the first gating circuitry of a prior stage in the plurality of series connected stages is applying one of the autozero and data load control signals to a respective prior row of pixels in the display device.

Claim 5

A row select circuit according to claim 3 , wherein stage in which the reset signal is applied immediately follows the stage in which the one of the autozero and data load control signals are applied in the plurality of series connected stages.

Claim 6

A row select circuit according to claim 3 , wherein stage in which the reset signal is applied is separated from the stage in which the one of the autozero and data load control signals are applied by at least one stage in the plurality of series connected stages.

Claim 7

A row select circuit according to claim 1 further including: third gating circuitry, responsive to an array select signal to apply selected ones of the plurality of broadcast control signals to all pixels in all rows in the display device.

Claim 8

A row select circuit according to claim 6 , wherein the pixels in the rows of pixels are subject to an autozero operation and a data load operation and the broadcast control signals include: a first control signal which causes the pixels in the selected row of pixels to perform the autozero operation while the array select signal selects all pixels in all rows of the display device and a second control signal occurring after the first control signal when the select signal selects individual rows of pixels, which causes the selected individual rows of pixels to perform the data load operation.

Claim 9

A row select circuit according to claim 1 , wherein the rows of pixels in the display exhibit different characteristics among a plurality of display devices and the broadcast control signals are adapted to achieve optimum performance for each display device.

Claim 10

A display device comprising: a polysilicon substrate; a plurality of rows of picture elements (pixels), implemented in the polysilicon substrate, each pixel including: an organic light emitting diode (OLED) display element; a first transistor configured as a current source, responsive to a control value to provide a controlled current to the OLED display element; a second transistor coupled to a select signal to store the control value into the pixel when the select signal is active; and a third transistor coupled to an illuminate signal to couple the controlled current to the OLED display element to illuminate the OLED display element when the select signal is not active; and a plurality of broadcast control signals including a broadcast illuminate control signal; a row select circuit, implemented on the polysilicon substrate, the row select circuit comprising a plurality of stages connected in series, each stage being coupled to a respective one of the rows of pixels to provide the select signal to the respective row of pixels and being coupled to receive the select signal from a previous stage of the series-connected stages as a signal to provide the select signal to the respective row of pixels, wherein the first stage is coupled to receive a select signal at the start of an image frame, wherein each stage includes: a fourth transistor, responsive to the select signal provided by the previous stage and a clock signal to generate the select signal for the respective row of pixels; a fifth transistor, responsive to the select signal for the row of pixels and to the broadcast illuminate signal to apply the illuminate control signal to the selected row of pixels.

Claim 11

A display device comprising: a polysilicon substrate; a plurality of rows of picture elements (pixels), implemented in the polysilicon substrate, each pixel including: an organic light emitting diode (OLED) display element; a first transistor configured as a current source, responsive to a control value to provide a controlled current to the OLED display element; a second transistor coupled to a select signal to store the control value into the pixel when the select signal is active; and a third transistor coupled to an illuminate signal to couple the controlled current to the OLED display element to illuminate the OLED display element when the select signal is not active; and a plurality of broadcast control signals including a broadcast illuminate control signal; a row select circuit, implemented on the polysilicon substrate, the row select circuit comprising a plurality of stages connected in series, each stage being coupled to a respective one of the rows of pixels to provide the select signal to the respective row of pixels and being coupled to receive the select signal from a previous stage of the series-connected stages as a signal to provide the select signal to the respective row of pixels, wherein the first stage is coupled to receive a select signal at the start of an image frame, wherein each stage includes: a fourth transistor, responsive to the select signal provided by the previous stage and a clock signal to generate the select signal for the respective row of pixels; a fifth transistor, responsive to the select signal for the row of pixels and to the broadcast illuminate signal to apply the illuminate control signal to the selected row of pixels.

Claim 12

A display device according to claim 9 wherein: each pixel further includes a sixth transistor coupled to the first transistor and to an autozero control signal to perform an autozero function on the first transistor; the plurality of broadcast control signals further includes a broadcast autozero signal; and each stage of the row select circuit further includes a seventh transistor, responsive to the select signal for the row of pixels and to the broadcast autozero signal for providing the autozero control signal to the sixth transistor of each pixel in the row of pixels.

Claim 13

A display device according to claim 10 wherein: the broadcast controls signals further include an array select signal; the row select circuit further includes: an eighth transistor, responsive to the array select signal to simultaneously apply the broadcast autozero signal to all pixels in all rows in the display device.