Bias circuit for a low voltage differential circuit

Claim 2

A bias circuit for a differential circuit, the differential circuit including a pair of differential transistors having control inputs receiving a differential signal and controlled current paths coupled between a source signal and ground, the bias circuit comprising: first and second transistors, each having a current path coupled between a first node and ground and a control input, the control inputs of the first and second transistors for receiving the differential signal; first and second impedance devices, each coupled between a control input of one of the first and second transistors and a second node; a reference current source, coupled to the source signal, that provides a reference current for the first node; and an amplifier having an input coupled to the first node and an output coupled to the second node.

Claim 3

The bias circuit of claim 1 , further comprising an inductor coupled in the current path between the first and second transistors and ground.

Claim 4

The bias circuit of claim 1 , further comprising a filter capacitor coupled between the first node and ground.

Claim 5

The bias circuit of claim 1 , wherein the first and second transistors each comprise a bipolar junction transistor (BJT) having a controlled current path between a collector and an emitter and having a base input.

Claim 6

The bias circuit of claim 4 , wherein the first and second transistors each comprise an NPN BJT.

Claim 7

The bias circuit of claim 5 , wherein the emitters of the differential transistors of the differential circuit and the first and second transistors are connected to ground.

Claim 8

The bias circuit of claim 4 , wherein the differential transistors of the differential circuit are also BJTs, further comprising: the first and second transistors having emitter area ratios that are matched to the emitter area ratios of the differential transistors of the differential circuit.

Claim 9

The bias circuit of claim 1 , wherein the first and second transistors comprise metal oxide semiconductor (MOS) type transistors.

Claim 10

The bias circuit of claim 1 , wherein the first and second impedance devices comprises resistors.

Claim 11

The bias circuit of claim 1 , wherein the first and second impedance devices comprises inductors.

Claim 12

The bias circuit of claim 1 , wherein the reference current of the reference current source is modulated.

Claim 13

The bias circuit of claim 1 , wherein the differential circuit comprises additional pairs of transistors to achieve multiple differential outputs.

Claim 14

A biased differential circuit, comprising: a first pair of differential transistors, each having a control input and first and second current terminals, wherein the first terminal of each is coupled to ground and wherein the control inputs of the pair of differential transistors receive a differential input signal; first and second resistors, each coupled between a source signal and the second current terminal of a respective one of the first pair of differential transistors, wherein the second current terminals of the first pair of differential transistors develops a differential output signal; a second pair of differential transistors, each having a control input and first and second current terminals coupled between a first node and ground, the control inputs of the second pair of differential transistors receiving the differential input signal; first and second impedance devices, each coupled between a control input of one of the second pair of differential transistors and a second node; a reference current source coupled to the source signal and provides a reference current for the first node; and an amplifier having an input coupled to the first node and an output driving the second node.

Claim 15

A biased differential circuit, comprising: a first pair of differential transistors, each having a control input and first and second current terminals, wherein the first terminal of each is coupled to ground and wherein the control inputs of the pair of differential transistors receive a differential input signal; first and second resistors, each coupled between a source signal and the second current terminal of a respective one of the first pair of differential transistors, wherein the second current terminals of the first pair of differential transistors develops a differential output signal; a second pair of differential transistors, each having a control input and first and second current terminals coupled between a first node and ground, the control inputs of the second pair of differential transistors receiving the differential input signal; first and second impedance devices, each coupled between a control input of one of the second pair of differential transistors and a second node; a reference current source coupled to the source signal and provides a reference current for the first node; and an amplifier having an input coupled to the first node and an output driving the second node.

Claim 16

The biased differential circuit of claim 13 , wherein each transistor of the first and second pair of differential transistors comprise NPN bipolar junction transistors having emitters connected to ground.

Claim 17

The biased differential circuit of claim 14 , wherein each of the transistors of the first and second pair of differential transistors have matching emitter area ratios.

Claim 18

The biased differential circuit of claim 14 , wherein the first and second impedance devices comprise matching resistors.

Claim 19

The biased differential circuit of claim 15 , further comprising: a filter capacitor coupled between the first node and ground.

Claim 20

The biased differential circuit of claim 17 , wherein the amplifier is a non-inverting amplifier.

Claim 21

The biased differential circuit of claim 13 , wherein each transistor of the first and second pair of differential transistors comprises an NPN bipolar junction transistors in which the first and second current terminals comprise emitter and collector terminals, respectively, the biased differential circuit further comprising: an inductor connected between the emitter terminal of each transistor of the first and second pairs of differential transistors and ground.

Claim 22

The biased differential circuit of claim 13 , wherein the first and second impedance devices comprise inductors.