US6338123B2
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Complete and concise remote (CCR) directory
Assignee: International Business Machines Corp
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Filing: 1999-03-31
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Granted: 2002-01-08
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Expires: 2019-03-31
Abstract
Abstract A method and structure for a system for maintaining coherence of cache lines in a shared memory multiplexor system comprises a system area network and a plurality of compute nodes connected to the system area network. Each of the computer nodes includes a local main memory, a local shared cache and a local coherence controller and computer nodes external to a given compute node include external shared caches and the coherence controller includes shadow directories, each corresponding to one of the external shared caches. Each of the shadow directories includes state information of the local main memory cached in the external shared caches. The shadow directories include only state information of the local main memory cached in the external shared caches.
Inventors
- 👤 Douglas J. Joseph
- 👤 Maged M. Michael
- 👤 Ashwini Nanda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:03
CPC Classifications
A; A47; A47J; A47J33/00; G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0822; A47J36/00; A47J36/24; A47J36/2477; C; C01; C01B; C01B32/00; C01B32/30
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
108 words
A system for maintaining coherence of cache lines in a shared memory multiplexor system comprising: a system area network; and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and a coherence controller, wherein said coherence controller includes shadow directories, each corresponding to shared caches of other compute nodes connected to said system area network, wherein each of said shadow directories includes only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system does not require a network protocol using a sealable coherent interface.
Claim 2
Independent Claim
108 words
A system for maintaining coherence of cache lines in a shared memory multiplexor system comprising: a system area network; and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and a coherence controller, wherein said coherence controller includes shadow directories, each corresponding to shared caches of other compute nodes connected to said system area network, wherein each of said shadow directories includes only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system does not require a network protocol using a sealable coherent interface.
Claim 3
Dependent Claim
38 words
The system in claim 1 , wherein each of said shadow directories includes a plurality of sets, each of said sets including a plurality of entries, each of said entries comprising a memory address of said main memory.
Claim 4
Dependent Claim
15 words
The system in claim 2 , wherein each entry includes tag bits and state bits.
Claim 5
Dependent Claim
23 words
The system in claim 1 , wherein said coherence controller maintains a dynamic full map directory of shared lines in said main memory.
Claim 6
Dependent Claim
105 words
A coherence controller for maintaining coherence of cache lines in a shared memory multiplexor system that includes a system area network and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and said coherence controller, said coherence controller comprising: shadow directories, each corresponding to shared caches of other compute nodes, wherein each of said shadow directories includes only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system area network does not require a network protocol using a sealable coherent interface.
Claim 7
Dependent Claim
105 words
A coherence controller for maintaining coherence of cache lines in a shared memory multiplexor system that includes a system area network and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and said coherence controller, said coherence controller comprising: shadow directories, each corresponding to shared caches of other compute nodes, wherein each of said shadow directories includes only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system area network does not require a network protocol using a sealable coherent interface.
Claim 8
Dependent Claim
39 words
The coherence controller in claim 5 , wherein each of said shadow directories includes a plurality of sets, each of said sets including a plurality of entries, each of said entries comprising a memory address of said main memory.
Claim 9
Dependent Claim
16 words
The coherence controller in claim 6 , wherein each entry includes tag bits and state bits.
Claim 10
Dependent Claim
24 words
The coherence controller in claim 5 , wherein said coherence controller maintains a dynamic full map directory of shared lines in said main memory.
Claim 11
Independent Claim
138 words
A method for maintaining coherence of cache lines in a shared memory multiplexor system that includes a system area network and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and a coherence controller, said method comprising: maintaining shadow directories in said coherence controller, each of said shadow directories corresponding to shared caches of other compute nodes; and maintaining state information of said main memory cached in said shared caches in corresponding ones of said shadow directories of said other compute nodes; wherein said maintaining of said state information maintains only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system area network does not require a network protocol using a sealable coherent interface.
Claim 12
Independent Claim
138 words
A method for maintaining coherence of cache lines in a shared memory multiplexor system that includes a system area network and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and a coherence controller, said method comprising: maintaining shadow directories in said coherence controller, each of said shadow directories corresponding to shared caches of other compute nodes; and maintaining state information of said main memory cached in said shared caches in corresponding ones of said shadow directories of said other compute nodes; wherein said maintaining of said state information maintains only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system area network does not require a network protocol using a sealable coherent interface.
Claim 13
Dependent Claim
40 words
The method in claim 9 , wherein said maintaining of said shadow directories includes maintaining a plurality of sets, each of said sets including a plurality of entries, each of said entries comprising a memory address of said main memory.
Claim 14
Dependent Claim
15 words
The method in claim 10 , wherein each entry includes tag bits and state bits.
Claim 15
Dependent Claim
30 words
The method in claim 9 , wherein said maintaining of said shadow directories in said coherence controller maintains a dynamic full map directory of shared lines in said main memory.
Claim 16
Dependent Claim
157 words
A program storage device readable by machine, tangibly embodying a program of instructions executable by said machine to perform method steps for maintaining coherence of cache lines in a shared memory multiplexor system that includes a system area network and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and a coherence controller, said method comprising: maintaining shadow directories in said coherence controller, each of said shadow directories corresponding to shared caches of other compute nodes; and maintaining state information of said main memory cached in said shared caches in corresponding ones of said shadow directories of said other compute nodes; wherein said maintaining of said state information maintains only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system area network does not require a network protocol using a sealable coherent interface.
Claim 17
Dependent Claim
157 words
A program storage device readable by machine, tangibly embodying a program of instructions executable by said machine to perform method steps for maintaining coherence of cache lines in a shared memory multiplexor system that includes a system area network and a plurality of compute nodes connected to said system area network, wherein each of said compute nodes includes a main memory, a shared cache and a coherence controller, said method comprising: maintaining shadow directories in said coherence controller, each of said shadow directories corresponding to shared caches of other compute nodes; and maintaining state information of said main memory cached in said shared caches in corresponding ones of said shadow directories of said other compute nodes; wherein said maintaining of said state information maintains only state information of said main memory cached in said shared caches of said other compute nodes, wherein said system area network does not require a network protocol using a sealable coherent interface.
Claim 18
Dependent Claim
42 words
The program storage device in claim 13 , wherein said maintaining of said shadow directories includes maintaining a plurality of sets, each of said sets including a plurality of entries, each of said entries comprising a memory address of said main memory.
Claim 19
Dependent Claim
17 words
The program storage device in claim 14 , wherein each entry includes tag bits and state bits.
Claim 20
Dependent Claim
32 words
The program storage device in claim 13 , wherein said maintaining of said shadow directories in said coherence controller maintains a dynamic full map directory of shared lines in said main memory.
References Cited (Backward Citations)
US5802578A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-01-07 | 2005-07-09 | 2006-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-01-07 | 2009-07-09 | 2010-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-01-07 | 2013-07-09 | 2014-01-08 | $7700.00 | Window Closed / Lapsed |