US6333247B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-step MOSFET gate formation for high-density devices
Assignee: International Business Machines Corp
•
Filing: 2000-02-10
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Granted: 2001-12-25
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Expires: 2020-02-10
Abstract
Abstract A method of manufacturing a metal-oxide-semiconductor field effect transistor MOSFET device gate includes patterning and etching the mesa of a gate material. A dielectric layer is formed on the mesa and is planarized using chemical mechanical polishing (CMP). The active gate dimension is patterned and etched to form source and drain wells that extend down to an active area on either side of the MOSFET gate. In one further embodiment, the wells are filled with metal and the metal is planarized. The MOSFET device, in one embodiment, includes source and drain wells equally spaced from the active gate.
Inventors
- 👤 Kevin K. Chan
- 👤 Erin C. Jones
- 👤 Paul M. Solomon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:08
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/017
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
99 words
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate material having a chemical mechanical polish stopping layer deposited thereon; said method comprising: patterning and etching a mesa of gate material larger in size than an active gate dimension; forming at least one dielectric layer on the mesa; planarizing the at least one dielectric layer to the polish stopping layer using chemical mechanical polishing; and patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the gate.
Claim 2
Independent Claim
99 words
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate material having a chemical mechanical polish stopping layer deposited thereon; said method comprising: patterning and etching a mesa of gate material larger in size than an active gate dimension; forming at least one dielectric layer on the mesa; planarizing the at least one dielectric layer to the polish stopping layer using chemical mechanical polishing; and patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the gate.
Claim 3
Dependent Claim
30 words
The method of claim 1 wherein the patterning and etching the gate further forms contact holes to source and drain at a bottom portion of said source and drain wells.
Claim 4
Dependent Claim
13 words
The method of claim 1 further comprising source and drain doping and silicidation.
Claim 5
Dependent Claim
33 words
The method of claim 1 wherein said patterning and etching the gate further forms a contact hole prior to source and drain doping at a bottom portion of said source and drain wells.
Claim 6
Dependent Claim
15 words
The method of claim 1 further comprising filling the source and drain wells with metal.
Claim 7
Dependent Claim
15 words
The method of claim 5 wherein said planarizing the metal comprises chemical mechanical polishing (CMP).
Claim 8
Independent Claim
121 words
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate having a starting substrate of a semiconductor wafer having gate material of a gate dielectric, gate conductor and a chemical mechanical polish stopping layer deposited thereon; said method comprising: patterning and etching a mesa of the gate material larger in size than an active gate dimension; forming at least one dielectric layer on the mesa of the gate material; planarizing the at least one dielectric layer to the polish stopping layer using chemical mechanical polishing; and patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the MOSFET gate.
Claim 9
Independent Claim
121 words
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate having a starting substrate of a semiconductor wafer having gate material of a gate dielectric, gate conductor and a chemical mechanical polish stopping layer deposited thereon; said method comprising: patterning and etching a mesa of the gate material larger in size than an active gate dimension; forming at least one dielectric layer on the mesa of the gate material; planarizing the at least one dielectric layer to the polish stopping layer using chemical mechanical polishing; and patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the MOSFET gate.
Claim 10
Dependent Claim
13 words
The method of claim 7 further comprising source and drain doping and silicidation.
Claim 11
Dependent Claim
27 words
The method of claim 7 wherein said patterning and etching the gate further forms a contact hole at a bottom portion of said source and drain wells.
Claim 12
Dependent Claim
31 words
The method of claim 7 wherein said patterning and etching the gate further forms a contact hole prior to source/drain doping at a bottom portion of said source and drain wells.
Claim 13
Dependent Claim
15 words
The method of claim 7 further comprising filling the source and drain wells with metal.
Claim 14
Independent Claim
120 words
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate having a topgate dimension, an active device gate dimension, said method comprising: supplying a semiconductor wafer having gate material of a dielectric, gate conductor and chemical mechanical polish stopping layers deposited thereon; patterning and etching a mesa of the gate material to a size larger than the active gate dimension; forming a dielectric layer on the mesa of the gate material; planarizing the dielectric layer to the polish stopping layer using chemical mechanical polishing; and patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the MOSFET gate.
Claim 15
Independent Claim
120 words
A method of manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) device gate, the gate having a topgate dimension, an active device gate dimension, said method comprising: supplying a semiconductor wafer having gate material of a dielectric, gate conductor and chemical mechanical polish stopping layers deposited thereon; patterning and etching a mesa of the gate material to a size larger than the active gate dimension; forming a dielectric layer on the mesa of the gate material; planarizing the dielectric layer to the polish stopping layer using chemical mechanical polishing; and patterning and etching the gate material to the active device gate dimension to form source and drain wells that extend to the active area on either side of the MOSFET gate.
Claim 16
Dependent Claim
13 words
The method of claim 12 further comprising source and drain doping and silicidation.
Claim 17
Dependent Claim
27 words
The method of claim 12 wherein said patterning and etching the gate further forms a contact hole at a bottom portion of said source and drain wells.
Claim 18
Dependent Claim
33 words
The method of claim 12 wherein said patterning and etching the gate further forms a contact hole prior to source and drain doping at a bottom portion of said source and drain wells.
Claim 19
Dependent Claim
15 words
The method of claim 8 further comprising filling the source and drain wells with metal.
Claim 20
Dependent Claim
16 words
A metal-oxide-semiconductor field effect transistor (MOSFET) device gate produced by the method of claim 5 .
Claim 21
Dependent Claim
16 words
A metal-oxide-semiconductor field effect transistor (MOSFET) device gate produced by the method of claim 11 .
Claim 22
Dependent Claim
16 words
A metal-oxide-semiconductor field effect transistor (MOSFET) device gate produced by the method of claim 16 .
References Cited (Backward Citations)
US6054355A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-24 | 2005-06-25 | 2005-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-24 | 2009-06-25 | 2009-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-24 | 2013-06-25 | 2013-12-25 | $7700.00 | Window Closed / Lapsed |