US6329935B1
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US
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Temporally separating and re-organizing data using two-stage interleaving and de-interleaving
Assignee: International Business Machines Corp
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Filing: 1999-12-22
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Granted: 2001-12-11
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Expires: 2019-12-22
Abstract
Abstract The present invention is a method and apparatus for temporally separating an input data stream in a transmit circuit and for re-organizing a temporally separated input data stream in a receive circuit. In the transmit circuit, a first interleaver interleaves the serial input data stream. A first converter is coupled to the first interleaver to convert the interleaved serial input data stream into groups of N-bit words where N is a positive integer. A second interleaver is coupled to the first converter to interleave the groups of N-bit words. A second converter is coupled to the second interleaver to convert the interleaved groups of N-bit words into a serial output data stream. The output data stream corresponds to the temporally separated input data stream. In the receive circuit, a first converter converts the serial input data stream into groups of N-bit words where N is a positive integer. A first de-interleaver is coupled to the first converter to de-interleave the groups of N-bit words. A second converter is coupled to the first de-interleaver to convert the de-interleaved groups of N-bit words into interleaved serial data. A second de-interleaver is coupled to the second converter to de-interleave the interleaved serial data into an output data stream. The output data stream corresponds to the re-organized input data stream.
Inventors
- 👤 Karen J. Stephen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:30
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/27
Claims Analysis
Total Claims: 66
Claim 1
Independent Claim
97 words
An apparatus to temporally separate an input data stream, the apparatus comprising: a first interleaver to interleave the serial input data stream; a first converter coupled to the first interleaver to convert the interleaved input data stream into groups of N-bit words, N being a positive integer; a second interleaver coupled to the first converter to interleave the groups of N-bit words; and a second converter coupled to the second interleaver to convert the interleaved groups of N-bit words into a serial output data stream, the output data stream corresponding to the temporally separated input data stream.
Claim 2
Independent Claim
97 words
An apparatus to temporally separate an input data stream, the apparatus comprising: a first interleaver to interleave the serial input data stream; a first converter coupled to the first interleaver to convert the interleaved input data stream into groups of N-bit words, N being a positive integer; a second interleaver coupled to the first converter to interleave the groups of N-bit words; and a second converter coupled to the second interleaver to convert the interleaved groups of N-bit words into a serial output data stream, the output data stream corresponding to the temporally separated input data stream.
Claim 3
Dependent Claim
87 words
The apparatus of claim 1 wherein the first interleaver comprises: a first write circuit coupled to a first memory to store the input data stream in the first memory in a bit normal order; and a first read circuit coupled to the first memory to read the stored input data stream from the first memory in a bit scrambled order at a first clock rate, the bit scrambled order separating adjacent bits in the input data stream, the separated bits corresponding to the interleaved input data stream.
Claim 4
Dependent Claim
23 words
The apparatus of claim 2 wherein the first converter comprises a serial-to-parallel converter to parallelize the input data stream into the N-bit words.
Claim 5
Dependent Claim
83 words
The apparatus of claim 3 wherein the second interleaver comprises: a second write circuit coupled to a second memory to store the groups of N-bit words in the second memory in a word normal order; and a second read circuit coupled to the second memory to read the stored groups of N-bit words in a word scrambled order at a second clock rate, the word scrambled order separating adjacent N-bit words, the separated N-bit words corresponding to the interleaved groups of N-bit words.
Claim 6
Dependent Claim
23 words
The apparatus of claim 4 wherein the second converter comprises a parallel-to-serial converter to serialize the N-bit words into the output data stream.
Claim 7
Dependent Claim
16 words
The apparatus of claim 5 wherein the first memory is substantially faster than the second memory.
Claim 8
Dependent Claim
16 words
The apparatus of claim 5 wherein the first memory is substantially smaller than the second memory.
Claim 9
Dependent Claim
18 words
The apparatus of claim 5 wherein the first clock rate is substantially faster than the second clock rate.
Claim 10
Dependent Claim
22 words
The apparatus of claim 8 wherein the first clock rate is faster than the second clock rate by a factor of N.
Claim 11
Dependent Claim
28 words
The apparatus of claim 5 wherein the first interleaver, the first converter, the second interleaver, the second converter, and the first memory are integrated in a single device.
Claim 12
Independent Claim
98 words
An apparatus to re-organize a temporally separated input data stream, the apparatus comprising: a first converter to convert the input data stream into groups of N-bit words, N being a positive integer; a first de-interleaver coupled to the first converter to de-interleave the groups of N-bit words; a second converter coupled to the first de-interleaver to convert the de-interleaved groups of N-bit words into interleaved serial data; and a second de-interleaver coupled to the second converter to de-interleave the interleaved serial data into an output data stream, the output data stream corresponding to the re-organized input data stream.
Claim 13
Independent Claim
98 words
An apparatus to re-organize a temporally separated input data stream, the apparatus comprising: a first converter to convert the input data stream into groups of N-bit words, N being a positive integer; a first de-interleaver coupled to the first converter to de-interleave the groups of N-bit words; a second converter coupled to the first de-interleaver to convert the de-interleaved groups of N-bit words into interleaved serial data; and a second de-interleaver coupled to the second converter to de-interleave the interleaved serial data into an output data stream, the output data stream corresponding to the re-organized input data stream.
Claim 14
Dependent Claim
23 words
The apparatus of claim 11 wherein the first converter comprises a serial-to-parallel converter to parallelize the input data stream into the N-bit words.
Claim 15
Dependent Claim
94 words
The apparatus of claim 12 wherein the first de-interleaver comprises: a first write circuit coupled to the first memory to store the groups of N-bit words in a first memory in a word scrambled order; and a first read circuit coupled to the first memory to read the stored groups of N-bit words from the first memory in a word normal order at a first clock rate, the word normal order re-arranging non-adjacent words in the groups of N-bit words, the re-arranged groups of N-bit words corresponding to the de-interleaved groups of N-bit words.
Claim 16
Dependent Claim
23 words
The apparatus of claim 13 wherein the second converter comprises a parallel-to-serial converter to serialize the N-bit words into the interleaved serial data.
Claim 17
Dependent Claim
83 words
The apparatus of claim 14 wherein the second de-interleaver comprises: a second write circuit coupled to a second memory to store the bit interleaved serial data in the second memory in a bit scrambled order; and a second read circuit coupled to the second memory to read the stored bit interleaved serial data in a bit normal order at a second clock rate, the bit normal order re-arranging the bit interleaved serial data, the re-arranged serial data corresponding to the output data stream.
Claim 18
Dependent Claim
16 words
The apparatus of claim 15 wherein the first memory is substantially slower than the second memory.
Claim 19
Dependent Claim
16 words
The apparatus of claim 15 wherein the first memory is substantially larger than the second memory.
Claim 20
Dependent Claim
18 words
The apparatus of claim 15 wherein the first clock rate is substantially slower than the second clock rate.
Claim 21
Dependent Claim
22 words
The apparatus of claim 18 wherein the first clock rate is slower than the second clock rate by a factor of N.
Claim 22
Dependent Claim
28 words
The apparatus of claim 15 wherein the first interleaver, the first converter, the second interleaver, the second converter, and the second memory are integrated in a single device.
Claim 23
Independent Claim
80 words
A method to temporally separate an input data stream, the method comprising: interleaving the input data stream by a first interleaver; converting the interleaved input data stream into groups of N-bit words by a first converter, N being a positive integer; interleaving the groups of N-bit words by a second interleaver; and converting the interleaved groups of N-bit words into an output data stream by a second converter, the output data stream corresponding to the temporally separated input data stream.
Claim 24
Independent Claim
80 words
A method to temporally separate an input data stream, the method comprising: interleaving the input data stream by a first interleaver; converting the interleaved input data stream into groups of N-bit words by a first converter, N being a positive integer; interleaving the groups of N-bit words by a second interleaver; and converting the interleaved groups of N-bit words into an output data stream by a second converter, the output data stream corresponding to the temporally separated input data stream.
Claim 25
Dependent Claim
79 words
The method of claim 21 wherein interleaving the input data stream comprises: storing the input data stream in the first memory in a bit normal order by a first write circuit; and reading the stored input data stream from the first memory in a bit scrambled order at a first clock rate by a first read circuit, the bit scrambled order separating adjacent bits in the input data stream, the separated bits corresponding to the interleaved input data stream.
Claim 26
Dependent Claim
26 words
The method of claim 22 wherein converting the interleaved input data stream comprises parallelizing the input data stream into the N-bit words by a serial-to-parallel converter.
Claim 27
Dependent Claim
76 words
The method of claim 23 wherein interleaving the groups of N-bit words comprises: storing the groups of N-bit words in the second memory in a word normal order by a second write circuit; and reading the stored groups of N-bit words in a word scrambled order at a second clock rate by a second read circuit, the word scrambled order separating adjacent N-bit words, the separated N-bit words corresponding to the interleaved groups of N-bit words.
Claim 28
Dependent Claim
27 words
The method of claim 24 wherein converting the interleaved groups of N-bit words comprises serializing the N-bit words into the output data stream by a parallel-to-serial converter.
Claim 29
Dependent Claim
16 words
The method of claim 25 wherein the first memory is substantially faster than the second memory.
Claim 30
Dependent Claim
16 words
The method of claim 25 wherein the first memory is substantially smaller than the second memory.
Claim 31
Dependent Claim
18 words
The method of claim 25 wherein the first clock rate is substantially faster than the second clock rate.
Claim 32
Dependent Claim
22 words
The method of claim 28 wherein the first clock rate is faster than the second clock rate by a factor of N.
Claim 33
Dependent Claim
28 words
The method of claim 25 wherein the first interleaver, the first converter, the second interleaver, the second converter, and the first memory are integrated in a single device.
Claim 34
Independent Claim
85 words
A method to re-organize a temporally separated input data stream, the method comprising: converting the input data stream into groups of N-bit words by a first converter, N being a positive integer; de-interleaving the groups of N-bit words by a first de-interleaver; converting the de-interleaved groups of N-bit words into bit interleaved serial data by a second converter; and de-interleaving the bit interleaved serial data into an output data stream by a second de-interleaver, the output data stream corresponding to the re-organized input data stream.
Claim 35
Independent Claim
85 words
A method to re-organize a temporally separated input data stream, the method comprising: converting the input data stream into groups of N-bit words by a first converter, N being a positive integer; de-interleaving the groups of N-bit words by a first de-interleaver; converting the de-interleaved groups of N-bit words into bit interleaved serial data by a second converter; and de-interleaving the bit interleaved serial data into an output data stream by a second de-interleaver, the output data stream corresponding to the re-organized input data stream.
Claim 36
Dependent Claim
25 words
The method of claim 31 wherein converting the input data stream comprises parallelizing the input data stream into the N-bit words by a serial-to-parallel converter.
Claim 37
Dependent Claim
87 words
The method of claim 32 wherein de-interleaving the groups of N-bit words comprises: storing the groups of N-bit words in a first memory in a word scrambled order by a first write circuit; and reading the stored groups of N-bit words from the first memory in a word normal order at a first clock rate by a first read circuit, the word normal order re-arranging non-adjacent words in the groups of N-bit words, the re-arranged groups of N-bit words corresponding to the de-interleaved groups of N-bit words.
Claim 38
Dependent Claim
28 words
The method of claim 33 wherein converting the de-interleaved groups of N-bit words comprises serializing the N-bit words into the bit interleaved serial data by a parallel-to-serial converter.
Claim 39
Dependent Claim
76 words
The method of claim 34 wherein de-interleaving the bit interleaved serial data comprises: storing the bit interleaved serial data in the second memory in a bit scrambled order by a second write circuit; and reading the stored bit interleaved serial data in a bit normal order at a second clock rate by a second read circuit, the bit normal order re-arranging the bit interleaved serial data, the re-arranged serial data corresponding to the output data stream.
Claim 40
Dependent Claim
16 words
The method of claim 35 wherein the first memory is substantially slower than the second memory.
Claim 41
Dependent Claim
16 words
The method of claim 35 wherein the first memory is substantially larger than the second memory.
Claim 42
Dependent Claim
18 words
The method of claim 35 wherein the first clock rate is substantially slower than the second clock rate.
Claim 43
Dependent Claim
22 words
The method of claim 38 wherein the first clock rate is slower than the second clock rate by a factor of N.
Claim 44
Dependent Claim
28 words
The method of claim 35 wherein the first interleaver, the first converter, the second interleaver, the second converter, and the second memory are integrated in a single device.
Claim 45
Independent Claim
125 words
A system comprising: a modulator to modulate an output data stream for transmission over a network channel; and a transmit circuit coupled to the modulator to temporally separate an input data stream to generate the output data stream, the transmit circuit comprising: a first interleaver to interleave the input data stream, a first converter coupled to the first interleaver to convert the interleaved input data stream into groups of N-bit words, N being a positive integer, a second interleaver coupled to the first converter to interleave the groups of N-bit words, and a second converter coupled to the second interleaver to convert the interleaved groups of N-bit words into the output data stream, the output data stream corresponding to the temporally separated input data stream.
Claim 46
Independent Claim
125 words
A system comprising: a modulator to modulate an output data stream for transmission over a network channel; and a transmit circuit coupled to the modulator to temporally separate an input data stream to generate the output data stream, the transmit circuit comprising: a first interleaver to interleave the input data stream, a first converter coupled to the first interleaver to convert the interleaved input data stream into groups of N-bit words, N being a positive integer, a second interleaver coupled to the first converter to interleave the groups of N-bit words, and a second converter coupled to the second interleaver to convert the interleaved groups of N-bit words into the output data stream, the output data stream corresponding to the temporally separated input data stream.
Claim 47
Dependent Claim
87 words
The system of claim 41 wherein the first interleaver comprises: a first write circuit coupled to a first memory to store the input data stream in the first memory in a bit normal order; and a first read circuit coupled to the first memory to read the stored input data stream from the first memory in a bit scrambled order at a first clock rate, the bit scrambled order separating adjacent bits in the input data stream, the separated bits corresponding to the interleaved input data stream.
Claim 48
Dependent Claim
23 words
The system of claim 42 wherein the first converter comprises a serial-to-parallel converter to parallelize the input data stream into the N-bit words.
Claim 49
Dependent Claim
83 words
The system of claim 43 wherein the second interleaver comprises: a second write circuit coupled to a second memory to store the groups of N-bit words in the second memory in a word normal order; and a second read circuit coupled to the second memory to read the stored groups of N-bit words in a word scrambled order at a second clock rate, the word scrambled order separating adjacent N-bit words, the separated N-bit words corresponding to the interleaved groups of N-bit words.
Claim 50
Dependent Claim
23 words
The system of claim 44 wherein the second converter comprises a parallel-to-serial converter to serialize the N-bit words into the output data stream.
Claim 51
Dependent Claim
16 words
The system of claim 45 wherein the first memory is substantially faster than the second memory.
Claim 52
Dependent Claim
16 words
The system of claim 45 wherein the first memory is substantially smaller than the second memory.
Claim 53
Dependent Claim
18 words
The system of claim 45 wherein the first clock rate is substantially faster than the second clock rate.
Claim 54
Dependent Claim
28 words
The system of claim 45 wherein the first interleaver, the first converter, the second interleaver, the second converter, and the first memory are integrated in a single device.
Claim 55
Dependent Claim
15 words
The system of claim 49 wherein the second memory is separated from the single device.
Claim 56
Independent Claim
118 words
A system comprising: a demodulator to demodulate a temporally separated input data stream; and a receive circuit coupled to the demodulator to re-organize the temporally separated input data stream, the receive circuit comprising: a first converter to convert the input data stream into groups of N-bit words, N being a positive integer, a first de-interleaver coupled to the first converter to de-interleave the groups of N-bit words, a second converter coupled to the first de-interleaver to convert the de-interleaved groups of N-bit words into interleaved serial data, and a second de-interleaver coupled to the second converter to de-interleave the interleaved serial data into an output data stream, the output data stream corresponding to the re-organized input data stream.
Claim 57
Independent Claim
118 words
A system comprising: a demodulator to demodulate a temporally separated input data stream; and a receive circuit coupled to the demodulator to re-organize the temporally separated input data stream, the receive circuit comprising: a first converter to convert the input data stream into groups of N-bit words, N being a positive integer, a first de-interleaver coupled to the first converter to de-interleave the groups of N-bit words, a second converter coupled to the first de-interleaver to convert the de-interleaved groups of N-bit words into interleaved serial data, and a second de-interleaver coupled to the second converter to de-interleave the interleaved serial data into an output data stream, the output data stream corresponding to the re-organized input data stream.
Claim 58
Dependent Claim
23 words
The system of claim 51 wherein the first converter comprises a serial-to-parallel converter to parallelize the input data stream into the N-bit words.
Claim 59
Dependent Claim
94 words
The system of claim 52 wherein the first de-interleaver comprises: a first write circuit coupled to the first memory to store the groups of N-bit words in a first memory in a word scrambled order; and a first read circuit coupled to the first memory to read the stored groups of N-bit words from the first memory in a word normal order at a first clock rate, the word normal order re-arranging non-adjacent words in the groups of N-bit words, the re-arranged groups of N-bit words corresponding to the de-interleaved groups of N-bit words.
Claim 60
Dependent Claim
23 words
The system of claim 53 wherein the second converter comprises a parallel-to-serial converter to serialize the N-bit words into the interleaved serial data.
Claim 61
Dependent Claim
79 words
The system of claim 54 wherein the second de-interleaver comprises: a second write circuit coupled to a second memory to store the interleaved serial data in the second memory in a bit scrambled order; and a second read circuit coupled to the second memory to read the stored interleaved serial data in a bit normal order at a second clock rate, the normal order re-arranging the interleaved serial data, the re-arranged serial data corresponding to the output data stream.
Claim 62
Dependent Claim
16 words
The system of claim 55 wherein the first memory is substantially slower than the second memory.
Claim 63
Dependent Claim
16 words
The system of claim 55 wherein the first memory is substantially larger than the second memory.
Claim 64
Dependent Claim
18 words
The system of claim 55 wherein the first clock rate is substantially slower than the second clock rate.
Claim 65
Dependent Claim
28 words
The system of claim 55 wherein the first interleaver, the first converter, the second interleaver, the second converter, and the second memory are integrated in a single device.
Claim 66
Dependent Claim
15 words
The system of claim 59 wherein the first memory is separated from the single device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-10 | 2005-06-11 | 2005-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-10 | 2009-06-11 | 2009-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-10 | 2013-06-11 | 2013-12-11 | $7700.00 | Window Closed / Lapsed |