US6329666B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same
Assignee: Round Rock Research LLC
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Filing: 2000-06-02
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Granted: 2001-12-11
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Expires: 2020-06-02
Abstract
Abstract An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
Inventors
- 👤 Trung T. Doan
- 👤 D. Mark Durcan
- 👤 Brent D. Gilgen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:05
CPC Classifications
H; H10; H10B; H10B63/00; H10B63/80; H10N; H10N70/00; H10N70/20; H10N70/231; H10D; H10D64/00; H10D64/01; H10D64/011; H10N70/011; H10N70/061; H10N70/063; H10N70/066; H10N70/801; H10N70/821; H10N70/826; H10N70/841; H10N70/8418; H10N70/881; H10N70/882; H10N70/8828; G; G11; G11C; G11C2213/00; G11C2213/50; G11C2213/52
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
123 words
A semiconductor memory device, said semiconductor memory device including at least one memory cell capable of being reversibly cycled between at least two different resistive states and comprising: a first conductive layer on a substrate, wherein said first conductive layer includes at least one raised portion; an insulative material over said first conductive layer; a recess in said insulative material over said at least one raised portion of said first conductive layer; a programmable resistive material formulated to be reversibly cycled between at least two different resistive states and disposed within said recess in direct contact with said at least one raised portion of said first conductive layer; and a second conductive layer in direct contact with and over said programmable resistive material.
Claim 2
Dependent Claim
123 words
A semiconductor memory device, said semiconductor memory device including at least one memory cell capable of being reversibly cycled between at least two different resistive states and comprising: a first conductive layer on a substrate, wherein said first conductive layer includes at least one raised portion; an insulative material over said first conductive layer; a recess in said insulative material over said at least one raised portion of said first conductive layer; a programmable resistive material formulated to be reversibly cycled between at least two different resistive states and disposed within said recess in direct contact with said at least one raised portion of said first conductive layer; and a second conductive layer in direct contact with and over said programmable resistive material.
Claim 3
Dependent Claim
17 words
The semiconductor memory device of claim 1 , wherein said programmable resistive material comprises a chalcogenide material.
Claim 4
Dependent Claim
28 words
The semiconductor memory device of claim 2 , wherein said chalcogenide material is selected from a group consisting of tellurium (Te), germanium (Ge), antimony (Sb), and combinations thereof.
Claim 5
Dependent Claim
50 words
The semiconductor memory device of claim 2 , wherein said chalcogenide material includes tellurium (Te), germanium (Ge), and antimony (Sb) in a ratio Te a Ge b Sb 100−(a+b) , where a, b, and 100−(a+b) are in atomic percentages which total 100% of the constituent elements and a≦70 and 15≦b≦50.
Claim 6
Dependent Claim
12 words
The semiconductor memory device of claim 4 , wherein 40≦a≦60 and 17≦b≦44.
Claim 7
Dependent Claim
117 words
A semiconductor memory cell, said semiconductor memory cell capable of being reversibly cycled between at least two different resistive states and comprising: a first conductive layer on a substrate, wherein said first conductive layer includes at least one raised portion; an insulative material over said first conductive layer; a recess in said insulative material over said at least one raised portion of said first conductive layer; a programmable resistive material formulated to be reversibly cycled between at least two different resistive states and disposed within said recess in direct contact with said at least one raised portion of said first conductive layer; and a second conductive layer in direct contact with and over said programmable resistive material.
Claim 8
Dependent Claim
117 words
A semiconductor memory cell, said semiconductor memory cell capable of being reversibly cycled between at least two different resistive states and comprising: a first conductive layer on a substrate, wherein said first conductive layer includes at least one raised portion; an insulative material over said first conductive layer; a recess in said insulative material over said at least one raised portion of said first conductive layer; a programmable resistive material formulated to be reversibly cycled between at least two different resistive states and disposed within said recess in direct contact with said at least one raised portion of said first conductive layer; and a second conductive layer in direct contact with and over said programmable resistive material.
Claim 9
Dependent Claim
17 words
The semiconductor memory cell of claim 6 , wherein said programmable resistive material comprises a chalcogenide material.
Claim 10
Dependent Claim
122 words
A computer having at least one semiconductor memory cell, said semiconductor memory cell capable of being reversibly cycled between at least two different resistive states and comprising: a first conductive layer on a substrate, wherein said first conductive layer includes at least one raised portion; an insulative material over said first conductive layer; a recess in said insulative material over said at least one raised portion of said first conductive layer; a programmable resistive material formulated to be reversibly cycled between at least two different resistive states and disposed within said recess in direct contact with said at least one raised portion of said first conductive layer; and a second conductive layer in direct contact with and over said programmable resistive material.
Claim 11
Dependent Claim
122 words
A computer having at least one semiconductor memory cell, said semiconductor memory cell capable of being reversibly cycled between at least two different resistive states and comprising: a first conductive layer on a substrate, wherein said first conductive layer includes at least one raised portion; an insulative material over said first conductive layer; a recess in said insulative material over said at least one raised portion of said first conductive layer; a programmable resistive material formulated to be reversibly cycled between at least two different resistive states and disposed within said recess in direct contact with said at least one raised portion of said first conductive layer; and a second conductive layer in direct contact with and over said programmable resistive material.
Claim 12
Dependent Claim
15 words
The computer of claim 8 , wherein said programmable resistive material comprises a chalcogenide material.
Claim 13
Dependent Claim
26 words
The computer of claim 9 , wherein said chalcogenide material is selected from the group consisting of tellurium (Te), germanium (Ge), antimony (Sb), and combinations thereof.
Claim 14
Dependent Claim
47 words
The computer of claim 9 , wherein said chalcogenide material includes tellurium (Te), germanium (Ge), antimony (Sb) in a ratio Te a Ge b Sb 100−(a+b) , where a, b, and 100−(a+b) are in atomic percentages which total 100% of the constituent elements and a≦70 and 15≦b≦50.
Claim 15
Dependent Claim
10 words
The computer of claim 11 , wherein 40≦a≦60 and 17≦b≦44.
References Cited (Backward Citations)
US4776678A
Cited
US5210598A
Cited
US5057451A
Cited
US5296716A
Cited
US5530378A
Cited
US5879955A
Cited
US5789277A
Cited
US6147395A
Cited
US6060723A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-10 | 2005-06-11 | 2005-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-10 | 2009-06-11 | 2009-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-10 | 2013-06-11 | 2013-12-11 | $7700.00 | Window Closed / Lapsed |