Interconnect delay driven placement and routing of an integrated circuit design

Claim 2

A computer implemented method for optimizing placement and routing of an integrated circuit design comprising: designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region; and automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through a logically equivalent component placed at a different location; and selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

Claim 3

The method of claim 1 , wherein said determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced comprises determining interconnect delays for a first plurality of interconnect routing paths interconnecting the first pin to a plurality of candidate locations, and for a second plurality of interconnect routing paths interconnecting the second pin to the same plurality of candidate locations, using performance driven routing.

Claim 4

The method of claim 2 , wherein said performance driven routing is performance driven maze routing.

Claim 5

The method of claim 2 , wherein said determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced further comprises summing the interconnect delays incurred between the first pin and a candidate location to the interconnect delay incurred between the second pin and the same candidate location.

Claim 6

The method of claim 4 , wherein said determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced further comprises summing the interconnect delay sum to the delay incurred at the re-placed component.

Claim 7

The method of claim 4 , wherein said determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced further comprises summing the interconnect delay sum to the delay incurred at the logically equivalent component disposed at the candidate location.

Claim 8

A computer implemented method for optimizing placement and routing of an integrated circuit design comprising: determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said determining comprises determining resistance for a plurality of candidate interconnect routings based at least in part on longitudinal distances of the candidate interconnect routings.

Claim 9

A computer implemented method for optimizing placement and routing of an integrated circuit design comprising: determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said determining comprises determining resistance for a plurality of candidate interconnect routings based at least in part on longitudinal distances of the candidate interconnect routings.

Claim 10

A computer implemented method for optimizing placement and routing of an integrated circuit design comprising: determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said determining comprises determining capacitance for a plurality of candidate interconnect routings based at least in part on disposition locations of ceiling and floor dense planes of the candidate interconnect routings.

Claim 11

A computer implemented method for optimizing placement and routing of an integrated circuit design comprising: determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said determining comprises determining capacitance for a plurality of candidate interconnect routings based at least in part on disposition locations of ceiling and floor dense planes of the candidate interconnect routings.

Claim 12

The method of claim 8 , wherein said determining of capacitance further comprises looking up capacitance values from a pre-determined capacitance table using a determined average inter-wire distance and various floor and ceiling dense plane combinations.

Claim 13

The method of claim 8 , wherein said determining of capacitance comprises determining congestion conditions for a plurality of interconnect planes.

Claim 14

An article of manufacture comprising: a recordable medium having recorded thereon a plurality of programming instructions for use to program a computer system to enable the computer system to be able to optimize placement and routing of an integrated circuit design, including designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region; and automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through the logically equivalent component placed at a different location; and selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

Claim 15

An article of manufacture comprising: a recordable medium having recorded thereon a plurality of programming instructions for use to program a computer system to enable the computer system to be able to optimize placement and routing of an integrated circuit design, including designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region; and automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through the logically equivalent component placed at a different location; and selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

Claim 16

The article of claim 11 , wherein said programming instructions further enable the computer system to determine interconnect delays for a first plurality of interconnect routing paths interconnecting the first pin to a plurality of candidate locations, and for a second plurality of interconnect routing paths interconnecting the second pin to the same plurality of candidate locations, using performance driven routing.

Claim 17

The article of claim 12 , wherein said programming instructions further enable the computer system to perform performance driven maze routing.

Claim 18

The article of claim 12 , wherein said programming instructions further enable the computer system to sum the interconnect delays incurred between the first pin and a candidate location to the interconnect delay incurred between the second pin and the same candidate location.

Claim 19

The article of claim 14 , wherein said programming instructions further enable the computer system to further sum the interconnect delay sum to the delay incurred at the re-placed component.

Claim 20

The article of claim 14 , wherein said programming instructions further enable the computer system to sum the interconnect delay sum to the delay incurred at the logically equivalent component disposed at the candidate location.

Claim 21

An article of manufacture comprising: a recordable medium having recorded thereon a plurality of programming instructions for use to program a computer system to enable the computer system to be able to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said programming instructions further enable the computer system to determine resistance for a plurality of candidate interconnect routings based at least in part on longitudinal distances of the candidate interconnect routings.

Claim 22

An article of manufacture comprising: a recordable medium having recorded thereon a plurality of programming instructions for use to program a computer system to enable the computer system to be able to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said programming instructions further enable the computer system to determine resistance for a plurality of candidate interconnect routings based at least in part on longitudinal distances of the candidate interconnect routings.

Claim 23

An article of manufacture comprising: a recordable medium having recorded thereon a plurality of programming instructions for use to program a computer system to enable the computer system to be able to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said programming instructions further enable the computer system to determine capacitance for a plurality of candidate interconnect routings based at least in part on disposition locations of ceiling and floor dense planes of the candidate interconnect routings.

Claim 24

An article of manufacture comprising: a recordable medium having recorded thereon a plurality of programming instructions for use to program a computer system to enable the computer system to be able to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein said programming instructions further enable the computer system to determine capacitance for a plurality of candidate interconnect routings based at least in part on disposition locations of ceiling and floor dense planes of the candidate interconnect routings.

Claim 25

The article of claim 18 , wherein said programming instructions further enable the computer system to look up capacitance values from a pre-determined capacitance table using a determined average inter-wire distance and various floor and ceiling dense plane combinations.

Claim 26

The article of claim 18 , wherein said programming instructions further enable the computer system to determine congestion conditions for a plurality of interconnect planes.

Claim 27

A computer system comprising: a storage medium having stored therein a plurality of programming instructions; a processor coupled to the storage medium to execute the programming instructions to optimize placement and routing of an integrated circuit design, including designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region; and automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through the logically equivalent component placed at a different location; and selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

Claim 28

A computer system comprising: a storage medium having stored therein a plurality of programming instructions; a processor coupled to the storage medium to execute the programming instructions to optimize placement and routing of an integrated circuit design, including designating a group of critical interconnect routing paths from a plurality of interconnect routing paths in a given region; and automatically determining, for each of the designated critical interconnect routing paths, if interconnect delay of a path segment connecting a first pin to a second pin through a component can be reduced by any of a plurality of different paths, said plurality of different paths interconnecting the first pin to the second pin through the component re-placed at a different location, through a logically equivalent component, and through the logically equivalent component placed at a different location; and selecting, for each of the designated critical interconnect routing paths, one of the plurality of different paths to interconnect the first pin to the second pin based primarily on an amount of interconnect delay reduction achieved.

Claim 29

The computer system of claim 21 , wherein the processor further executes the programming instructions to determine interconnect delays for a first plurality of interconnect routing paths interconnecting the first pin to a plurality of candidate locations, and for a second plurality of interconnect routing paths interconnecting the second pin to the same plurality of candidate locations, using performance driven routing.

Claim 30

The computer system of claim 22 , wherein the processor further executes the programming instructions to perform performance driven maze routing.

Claim 31

The computer system of claim 22 , wherein the processor further executes the programming instructions to sum the interconnect delays incurred between the first pin and a candidate location to the interconnect delay incurred between the second pin and the same candidate location.

Claim 32

The computer system of claim 24 , wherein the processor further executes the programming instructions to further sum the interconnect delay sum to the delay incurred at the re-placed component.

Claim 33

The computer system of claim 24 , wherein the processor further executes the programming instructions to sum the interconnect delay sum to the delay incurred at the logically equivalent component disposed at the candidate location.

Claim 34

A computer system comprising: a storage medium having stored therein a plurality of programming instructions; a processor coupled to the storage medium to execute the programming instructions to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein the processor further executes the programming instructions to determine resistance for a plurality of candidate interconnect routings based at least in part on longitudinal distances of the candidate interconnect routings.

Claim 35

A computer system comprising: a storage medium having stored therein a plurality of programming instructions; a processor coupled to the storage medium to execute the programming instructions to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein the processor further executes the programming instructions to determine resistance for a plurality of candidate interconnect routings based at least in part on longitudinal distances of the candidate interconnect routings.

Claim 36

A computer system comprising: a storage medium having stored therein a plurality of programming instructions; a processor coupled to the storage medium to execute the programming instructions to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein the processor further executes the programming instructions to determine capacitance for a plurality of candidate interconnect routings based at least in part on disposition locations of ceiling and floor dense planes of the candidate interconnect routings.

Claim 37

A computer system comprising: a storage medium having stored therein a plurality of programming instructions; a processor coupled to the storage medium to execute the programming instructions to optimize placement and routing of an integrated circuit design, including determining if interconnect delay of a critical interconnect routing path segment connecting a first pin to a second pin through a component can be reduced by a different interconnect routing path interconnecting the first pin to the second through the component re-placed at a different location, and alternatively through a logically equivalent component placed at a different location; and selecting one of such different interconnect routing paths to interconnect the first pin to the second pin based primarily on the amount of interconnect delay reduction achieved, wherein the processor further executes the programming instructions to determine capacitance for a plurality of candidate interconnect routings based at least in part on disposition locations of ceiling and floor dense planes of the candidate interconnect routings.

Claim 38

The computer system of claim 28 , wherein the processor further executes the programming instructions to look up capacitance values from a pre-determined capacitance table using a determined average inter-wire distance and various floor and ceiling dense plane combinations.

Claim 39

The computer system of claim 28 , wherein the processor further executes the programming instructions to determine congestion conditions for a plurality of interconnect planes.