Cipher core in a content protection system

Claim 3

The apparatus of claim 1 , wherein the key generator comprises a feedback register to store ciphertext feedback data received from the encryption function for use by the key generator in generating the encryption function key.

Claim 4

The apparatus of claim 1 , wherein the controller controls ten rounds of encryption processing for the block.

Claim 5

The apparatus of claim 1 , wherein the encryption function encrypts the block according to a M6-S56 cipher.

Claim 6

The apparatus of claim 1 , wherein the encryption function comprises combinatorial logic.

Claim 7

The apparatus of claim 1 , wherein the encryption function comprises sequential logic.

Claim 8

The apparatus of claim 1 , wherein the block assembler comprises circuitry to assemble a block from multiple data words and to initiate processing by the controller whenever a block is ready to be processed.

Claim 9

The apparatus of claim 1 , wherein the controller comprises a timer to set a duration for each round and a state machine to control processing of the rounds.

Claim 10

The apparatus of claim 1 , wherein the block transmitter comprises circuitry to disassemble an encrypted block into multiple encrypted data words and to transfer the encrypted data words to a bus interface.

Claim 13

The apparatus of claim 10 , wherein the first set of rounds comprises rounds one through five of a cipher and the second set of rounds comprises rounds six through ten of the cipher.

Claim 14

The apparatus of claim 10 , wherein the encryption functions comprise combinatorial logic.

Claim 15

The apparatus of claim 10 , wherein the encryption functions comprise sequential logic.

Claim 16

The apparatus of claim 10 , wherein the first controller comprises a first timer to set a first duration for each of rounds one through five and a first state machine to control rounds one through five.

Claim 17

The apparatus of claim 10 , wherein the second controller comprises a second timer to set a second duration for each of rounds six through ten and a second state machine to control rounds six through ten.

Claim 18

A cipher system comprising: a cipher core to encrypt plaintext data into ciphertext data; and a bus interface coupled to the cipher core to transfer the ciphertext data to a bus; wherein the cipher core comprises: a block assembler to receive words of plaintext data from the message parser in an encrypt data message and to assemble the words into a block; an encryption function coupled to the block assembler to encrypt the block into ciphertext data based on an encryption function key; a block transmitter coupled to the encryption function to receive the encrypted block, to disassemble the encrypted block into ciphertext data words, and to forward the ciphertext data words to the bus interface; a controller coupled to the block assembler, the encryption function, and the block transmitter to control multiple rounds of encryption by the encryption function for the block; and a key generator coupled to the message parser and the encryption function to accept a content key from the message parser and to generate the encryption function key from the content key, the encryption function key being used by the encryption function to encrypt the blocks.

Claim 19

A cipher system comprising: a cipher core to encrypt plaintext data into ciphertext data; and a bus interface coupled to the cipher core to transfer the ciphertext data to a bus; wherein the cipher core comprises: a block assembler to receive words of plaintext data from the message parser in an encrypt data message and to assemble the words into a block; an encryption function coupled to the block assembler to encrypt the block into ciphertext data based on an encryption function key; a block transmitter coupled to the encryption function to receive the encrypted block, to disassemble the encrypted block into ciphertext data words, and to forward the ciphertext data words to the bus interface; a controller coupled to the block assembler, the encryption function, and the block transmitter to control multiple rounds of encryption by the encryption function for the block; and a key generator coupled to the message parser and the encryption function to accept a content key from the message parser and to generate the encryption function key from the content key, the encryption function key being used by the encryption function to encrypt the blocks.

Claim 20

The cipher system of claim 16 , wherein the bus comprises an IEEE 1394 bus.

Claim 21

The cipher system of claim 16 , wherein the cipher core comprises a M6-S56 cipher.

Claim 22

The cipher system of claim 16 , further comprising a processor interface coupled to the message parser to receive messages from a processor.

Claim 23

The cipher system of claim 16 , wherein the key generator comprises a feedback register to receive ciphertext feedback data from the encryption function for use by the key generator in generating the encryption function key.

Claim 24

A cipher system comprising: a cipher core to encrypt plaintext data into ciphertext data; and a bus interface coupled to the cipher core to transfer the ciphertext data to a bus; wherein the cipher core comprises: a block assembler to receive words of plaintext data and to assemble the words into a block; first and second encryption functions coupled to the block assembler to encrypt the block into ciphertext data based on an encryption function key; a block transmitter coupled to the first and second encryption functions to receive the encrypted block and to disassemble the encrypted block into ciphertext data words; a first controller coupled to the block assembler and the first encryption function to control a first set of rounds of encryption for the block by the first encryption function; and a second controller coupled to the first controller and the second encryption function to control a second set of rounds of encryption for the block by the second encryption function.

Claim 25

A cipher system comprising: a cipher core to encrypt plaintext data into ciphertext data; and a bus interface coupled to the cipher core to transfer the ciphertext data to a bus; wherein the cipher core comprises: a block assembler to receive words of plaintext data and to assemble the words into a block; first and second encryption functions coupled to the block assembler to encrypt the block into ciphertext data based on an encryption function key; a block transmitter coupled to the first and second encryption functions to receive the encrypted block and to disassemble the encrypted block into ciphertext data words; a first controller coupled to the block assembler and the first encryption function to control a first set of rounds of encryption for the block by the first encryption function; and a second controller coupled to the first controller and the second encryption function to control a second set of rounds of encryption for the block by the second encryption function.