Write-once thin-film memory

Claim 2

A data storage device comprising: a group of thin-film memory cells; and a circuit for applying write potentials to at least some of the memory cells; the memory cells having thin-film barriers that are damaged when the write potentials are applied.

Claim 3

The device of claim 1 , wherein the group is an array of memory cells.

Claim 4

The device of claim 2 , wherein the circuit applies first and second write potentials to word and bit lines crossing a first group of memory cells during re-write operations, the first and second write potentials not causing dielectric breakdown in selected memory cells of the first group; and wherein the circuit applies third and fourth write potentials to word and bit lines crossing a second group of memory cells during write-once operations, the third and fourth write potentials causing dielectric breakdown in selected memory cells of the second group.

Claim 5

The device of claim 3 , wherein the circuit includes first sense amplifiers for the first group of memory cells and second sense amplifiers for the second group of memory cells, the first and second sense amplifiers sensing different resistance states during read operations.

Claim 6

The device of claim 3 , wherein the memory cells of the first group can be switched between a nominal resistance corresponding to a first logic value and a second resistance state corresponding to a second logic value; wherein the memory cells of the second group have either the nominal resistance corresponding to the first logic value or a third resistance corresponding to the second logic value; and wherein the nominal, second and third resistances are different.

Claim 7

The device of claim 2 , wherein at least some of the memory cells include memory elements and resistive elements, each resistive element being connected in series with a memory element.

Claim 8

The device of claim 6 , wherein the resistive elements have a resistance between about 0.1% and 50% of nominal memory cell resistance.

Claim 9

The device of claim 2 , wherein the circuit applies an equal potential to a selected bit line and a subset of unselected lines during read operations.

Claim 10

The device of claim 2 , further comprising a plurality of word and bit lines, each memory cell being at a cross point of a word line and a bit line; and wherein the circuit includes: a sense amplifier; a first switch for each word line, each first switch connecting a selected row to ground for both read and write operations, connecting an unselected row to an array voltage during read operations, and connecting unselected rows to a half-select write voltage during write-once operations; and a second switch for each bit line, each second switch connecting a selected bit line to an input of the sense amplifier during read and write operations, connecting unselected bit lines to the array voltage during read operations, and connecting the unselected bit lines to a half-select voltage during write-once operations.

Claim 11

The device of claim 9 , wherein the sense amplifier senses the resistance states of selected memory cells during read operations and applies re-write potentials to selected memory cells during re-write operations; and wherein during write-once operations, the sense amplifier applies a ground potential to write a logic ‘0’ to selected memory cells and twice the half-select voltage to write a logic ‘1’ to selected memory cells.

Claim 12

The device of claim 2 , wherein at least some memory cells include memory elements and access transistors for the memory elements.

Claim 13

The device of claim 11 , wherein voltages applied to the memory elements are controlled by controlling gate voltages of the access transistors.

Claim 14

The device of claim 11 , wherein the circuit includes a sense amplifier including a ratioed current mirror and a buffer amplifier for sensing a resistance state of a selected memory cell.

Claim 15

The device of claim 1 , wherein the group includes registers of write-once memory cells.

Claim 16

The device of claim 14 , wherein each memory cell includes a memory element, and an access transistor for the memory element.

Claim 17

The device of claim 15 , wherein voltages applied to the memory elements are limited by controlling gate voltages of the access transistors.

Claim 18

The device of claim 14 , wherein the circuit includes a differential amplifier and a reference element, the differential amplifier indicating a difference between sense and reference currents flowing through selected memory cells and the reference elements during read operations on the selected memory cells, the differences indicating the resistance state of the selected memory cells.

Claim 19

The device of claim 14 , wherein the circuit includes a differential amplifier having a node coupled to the memory cell, the differential amplifier generating a full write voltage during a write operation, the circuit further including a transistor for pulling down the node according to a state of an input line.

Claim 20

The device of claim 1 , wherein the memory cells are MRAM cells.

Claim 21

The device of claim 1 , wherein the memory cells include spin-dependent tunneling junctions.

Claim 22

A data storage device comprising: a memory cell array including a first group of thin-film memory cells and a second group of thin-film memory cells; and a plurality of word lines and bit lines for the array, each memory cell being at a cross point of a word line and a bit line; and a circuit for applying first and second write potentials to word and bit lines crossing the first group of memory cells during re-write operations, the first and second write potentials not causing dielectric breakdown in selected memory cells of the first group, the circuit applying third and fourth write potentials to word and bit lines crossing the second group of memory cells during write-once operations, the third and fourth write potentials causing dielectric breakdown in selected memory cells of the second group.

Claim 23

A data storage device comprising: a memory cell array including a first group of thin-film memory cells and a second group of thin-film memory cells; and a plurality of word lines and bit lines for the array, each memory cell being at a cross point of a word line and a bit line; and a circuit for applying first and second write potentials to word and bit lines crossing the first group of memory cells during re-write operations, the first and second write potentials not causing dielectric breakdown in selected memory cells of the first group, the circuit applying third and fourth write potentials to word and bit lines crossing the second group of memory cells during write-once operations, the third and fourth write potentials causing dielectric breakdown in selected memory cells of the second group.

Claim 24

A data storage device comprising: a plurality of registers, each register including a thin-film memory element and an access transistor; and a circuit for applying write potentials to at least some of the memory cells, the memory cells having thin-film barriers that are damaged when the write potentials are applied.

Claim 25

A data storage device comprising: a plurality of registers, each register including a thin-film memory element and an access transistor; and a circuit for applying write potentials to at least some of the memory cells, the memory cells having thin-film barriers that are damaged when the write potentials are applied.

Claim 26

The device of claim 22 , wherein the circuit includes a differential amplifier for each register, each different amplifier having a first node coupled to the element via the access transistor memory cell, each differential amplifier having a second node coupled to a reference cell, each differential amplifier generating a full write voltage during a write operation, the circuit further including a pull-down transistor for each register, each pull-down transistor pulling down the first node according to a state of a write signal.

Claim 27

The device of claim 22 , wherein the circuit includes a differential amplifier for each register, each different amplifier having a first node coupled to a corresponding element via the access transistor memory cell, each differential amplifier having a second node coupled to a corresponding reference cell; and wherein the circuit uses a differential amplifier to perform a read operation on a selected register by bringing the nodes of the differential amplifier to a low voltage, then equalizing the voltages on the nodes and connecting the nodes to the corresponding memory element and reference cell, then allowing a differential voltage across the nodes to develop, then isolating the differential amplifier and then forcing the nodes to a full swing voltage, whereby at least one of the nodes indicates a sensed resistance state of the selected register.