Calibrating data strobe signal using adjustable delays with feedback

Claim 3

The apparatus of claim 1 wherein the delay circuit comprises: a plurality of delay elements, each having an adjustable delay, to provide the plurality of delay strobe signals in the operational mode and the calibration signal in the calibration mode from the reference signal via the plurality of delay elements; and a plurality of multiplexers coupled to the plurality of delay elements, the plurality of multiplexers including a first multiplexer and one less than plurality of multiplexers, each of the plurality of multiplexers selecting one of a corresponding data strobe signal from the plurality of data strobe signals and a cascading signal, the cascading signal being the reference signal for the first multiplexer, the cascading signal being a delay output signal from a previous delay element for the one less than plurality of multiplexers.

Claim 4

The apparatus of claim 2 wherein the interval is dependent on a sum of the delays of the plurality of delay elements.

Claim 5

The apparatus of claim 2 wherein the calibrator comprises: an edge detector to provide a phase difference between edges of the reference signal and the calibration signal, the phase difference corresponding to the interval; and a delay counter coupled to the edge detector to generate a delay control signal based on the phase difference, the delay control signal adjusting the plurality of delay elements.

Claim 6

The apparatus of claim 4 wherein the timing relationship corresponds to a coincidence of edges of the reference signal and the calibration signal when the phase difference is approximately equal to zero.

Claim 7

The apparatus of claim 1 wherein the plurality of data are provided in a read mode of a memory device.

Claim 8

The apparatus of claim 6 wherein the memory device is a double data rate (DDR) random access memory (RAM).

Claim 9

The apparatus of claim 7 wherein the calibration mode occurs during one of a refresh time and a write cycle time of the DDR RAM.

Claim 12

The method of claim 9 wherein generating the plurality of delay strobe signals comprises: providing the plurality of delay strobe signals in the operational mode and the calibration signal in the calibration mode from the reference signal via the plurality of delay elements; and selecting one of a corresponding data strobe signal from the plurality of data strobe signals and a cascading signal by plurality of multiplexers, the cascading signal being the reference signal for a first multiplexer, the cascading signal being a delay output signal from a previous delay element for one less than plurality of multiplexers.

Claim 13

The method of claim 10 wherein the interval is dependent on a sum of the delays of the plurality of delay elements.

Claim 14

The method of claim 10 wherein the step of adjusting comprises: providing a phase difference between edges of the reference signal and the calibration signal, the phase difference corresponding to the interval; and generating a delay control signal based on the phase difference, the delay control signal adjusting the plurality of delay elements.

Claim 15

The method of claim 12 wherein the timing relationship corresponds to a coincidence of edges of the reference signal and the calibration signal when the phase difference is approximately equal to zero.

Claim 16

The method of claim 9 wherein the plurality of data are provided in a read mode of a memory device.

Claim 17

The method of claim 14 wherein the memory device is a double data rate (DDR) random access memory (RAM).

Claim 18

The method of claim 15 wherein the calibration mode occurs during one of a refresh time and a write cycle time of the DDR RAM.

Claim 19

A circuit comprising: a plurality of registers to receive a plurality of data; and a delay controller coupled to the plurality of registers, the delay controller comprising: a delay circuit to generate a plurality of delay strobe signals from a plurality of data strobe signals during an operational mode and a calibration signal from a reference signal by an interval during a calibration mode, the plurality of delay strobe signals clocking the plurality of data into the plurality of registers, and a calibrator coupled to the delay circuit to adjust the interval according to a timing relationship between the calibration signal and the reference signal.

Claim 20

A circuit comprising: a plurality of registers to receive a plurality of data; and a delay controller coupled to the plurality of registers, the delay controller comprising: a delay circuit to generate a plurality of delay strobe signals from a plurality of data strobe signals during an operational mode and a calibration signal from a reference signal by an interval during a calibration mode, the plurality of delay strobe signals clocking the plurality of data into the plurality of registers, and a calibrator coupled to the delay circuit to adjust the interval according to a timing relationship between the calibration signal and the reference signal.

Claim 21

The circuit of claim 17 wherein the delay circuit comprises: a plurality of delay elements, each having an adjustable delay, to provide the plurality of delay strobe signals in the operational mode and the calibration signal in the calibration mode from the reference signal via the plurality of delay elements; and a plurality of multiplexers coupled to the plurality of delay elements, the plurality of multiplexers including a first multiplexer and one less than plurality of multiplexers, each of the plurality of multiplexers selecting one of a corresponding data strobe signal from the plurality of data strobe signals and a cascading signal, the cascading signal being the reference signal for the first multiplexer, the cascading signal being a delay output signal from a previous delay element for the one less than plurality of multiplexers.

Claim 22

The circuit of claim 18 wherein the interval is dependent on a sum of the delays of the plurality of delay elements.

Claim 23

The circuit of claim 18 wherein the calibrator comprises: an edge detector to provide a phase difference between edges of the reference signal and the calibration signal, the phase difference corresponding to the interval; and a delay counter coupled to the edge detector to generate a delay control signal based on the phase difference, the delay control signal adjusting the plurality of delay elements.

Claim 24

The circuit of claim 20 wherein the timing relationship corresponds to a coincidence of edges of the reference signal and the calibration signal when the phase difference is approximately equal to zero.

Claim 25

The circuit of claim 17 wherein the plurality of data are provided in a read mode of a memory device.

Claim 26

The circuit of claim 22 wherein the memory device is a double data rate (DDR) random access memory (RAM).

Claim 27

The circuit of claim 23 wherein the calibration mode occurs during one of a refresh time and a write cycle time of the DDR RAM.