US6314490B1
Expired / Lapsed
US
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Method and apparatus for memory addressing
Assignee: ATI Technologies ULC
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Filing: 1999-11-02
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Granted: 2001-11-06
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Expires: 2019-11-02
Abstract
Abstract A method and apparatus for addressing memory in a processing system that includes a cache structure and supports multiple data streams is presented. The cache structure may be an N-way (where N is a number) cache that includes multiple sets or may be a simple set associative cache. A portion of the cache is divided into a number of blocks where each of the blocks is used to store data associated with a particular stream. Thus, different streams utilize different portions of the cache structure. In order to support the division of the stream portion of the cache into multiple blocks, addresses corresponding to stream data operations are modified for use in addressing the cache. The modification of the addresses includes the shifting bits of a shifted portion which may be located in the middle bit portion of the of the address by N bits and inserting an N-bit wide more significant portion of the address into the less significant position that lies between the shifted portion after shifting and a least significant portion. If it is determined that an access to the cache requires a subsequent access to another memory structure such as the main memory, the address used to address the cache is further modified to produce a address for accessing the other memory structure. Preferably, this includes discarding the more significant portion that was relocated to the less significant position and shifting the shifted portion back to its original position. The most significant portion of the address is then filled with a predetermined bit pattern to facilitate addressing the other memory structure.
Inventors
- 👤 Stephen L. Morein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
98 words
A method for addressing memory, comprising: dividing a first memory into a plurality of sets; receiving an address corresponding to a first memory access; modifying the address such that a more significant portion of the address is exchanged with a shifted portion which has a less significant position in the address, the shifted portion identifying a particular set in the first memory and the more significant portion identifying a block in the particular set, wherein modifying the address produces a first memory address; and performing the first memory access to the first memory using the first memory address.
Claim 2
Independent Claim
98 words
A method for addressing memory, comprising: dividing a first memory into a plurality of sets; receiving an address corresponding to a first memory access; modifying the address such that a more significant portion of the address is exchanged with a shifted portion which has a less significant position in the address, the shifted portion identifying a particular set in the first memory and the more significant portion identifying a block in the particular set, wherein modifying the address produces a first memory address; and performing the first memory access to the first memory using the first memory address.
Claim 3
Dependent Claim
58 words
The method of claim 1 , wherein modifying the address further comprises left-shifting the shifted portion of the address by N bits and inserting the more significant portion in the less significant position, wherein the less significant position lies between the shifted portion after shifting and a least significant portion, wherein the more significant portion includes N bits.
Claim 4
Dependent Claim
13 words
The method of claim 2 , wherein the first memory is a cache.
Claim 5
Dependent Claim
15 words
The method of claim 3 , wherein 2N stream buffers are maintained within the cache.
Claim 6
Dependent Claim
21 words
The method of claim 4 , wherein performing the first memory access further comprises accessing data relating to video graphics processing.
Claim 7
Dependent Claim
29 words
The method of claim 5 , wherein the data relating to video graphics processing includes at least one of color data, primitive vertex coordinate data, and texture mapping data.
Claim 8
Dependent Claim
57 words
The method of claim 3 , further comprises: determining that a second memory access to a second memory is required based on the first memory access; modifying one of the address and the first memory address to produce a second memory address; and performing the second memory access to the second memory using the second memory address.
Claim 9
Dependent Claim
53 words
The method of claim 7 , wherein modifying the first memory address to produce the second memory access includes: discarding the more significant portion of the address; right-shifting the shifted portion of the address by N bits; and filling a most significant portion of the second memory address with a predetermined bit pattern.
Claim 10
Dependent Claim
26 words
The method of claim 1 , wherein the more significant portion of the address is derived from a memory instruction corresponding to the first memory access.
Claim 11
Dependent Claim
160 words
A processing circuit, comprising: a memory; a cache, wherein the cache is divided into a plurality of sets, each set including a plurality of blocks used for stream data caching, wherein the cache stores copies of at least of a portion of data stored in the memory; a processor, wherein the processor issues a memory access request that includes an address; and a cache control block operably coupled to the cache, the processor, and the memory, wherein the cache control block performs the functions of: receiving the address from the processor; modifying the address such that a more significant portion of the address is exchanged with a shifted portion which has a less significant position in the address, the shifted portion identifying a particular set in the cache and the more significant portion defines a block within the particular set, wherein modifying the address produces a cache address; and performing a cache access to the cache using the cache address.
Claim 12
Dependent Claim
160 words
A processing circuit, comprising: a memory; a cache, wherein the cache is divided into a plurality of sets, each set including a plurality of blocks used for stream data caching, wherein the cache stores copies of at least of a portion of data stored in the memory; a processor, wherein the processor issues a memory access request that includes an address; and a cache control block operably coupled to the cache, the processor, and the memory, wherein the cache control block performs the functions of: receiving the address from the processor; modifying the address such that a more significant portion of the address is exchanged with a shifted portion which has a less significant position in the address, the shifted portion identifying a particular set in the cache and the more significant portion defines a block within the particular set, wherein modifying the address produces a cache address; and performing a cache access to the cache using the cache address.
Claim 13
Dependent Claim
67 words
The processing circuit of claim 10 , wherein the cache control block modifies the address to produce the cache address by left-shifting the shifted portion of the address by N bits and inserting the more significant portion in the less significant position, wherein the less significant portion lies between the shifted portion after shifting and a least significant portion, wherein the more significant portion includes N bits.
Claim 14
Dependent Claim
58 words
The processing circuit of claim 11 , wherein the cache control block performs the additional functions of: determining that a memory access to the memory is required based on the cache access; modifying one of the address and the cache address to produce a memory address; and performing the memory access to the memory using the memory address.
Claim 15
Dependent Claim
55 words
The processing circuit of claim 12 , wherein the cache control block modifies the cache address to produce the memory address by discarding the more significant portion of the address, right-shifting the shifted portion of the address by N bits, and filling a most significant portion of the memory address with a predetermined bit pattern.
Claim 16
Dependent Claim
15 words
The processing circuit of claim 10 , wherein the processor is a video graphics processor.
Claim 17
Dependent Claim
37 words
The processing circuit of claim 14 , wherein stream data stored in the blocks of the cache includes video graphics processing data that includes at least one of color data, primitive vertex data, and texture mapping data.
Claim 18
Dependent Claim
118 words
A processor, comprising: a processing module; and instruction memory operably coupled to the processing module, wherein the instruction memory stores operating instructions that, when executed by the processing module, cause the processing module to perform functions that include: modifying an address received for a first memory access such that a more significant portion of the address is exchanged with a shifted portion which has a less significant position in the address, the shifted portion identifying a particular set in a first memory and the more significant portion identifying a block in the particular set, wherein modifying the address produces a first memory address; and performing the first memory access to the first memory using the first memory address.
Claim 19
Dependent Claim
118 words
A processor, comprising: a processing module; and instruction memory operably coupled to the processing module, wherein the instruction memory stores operating instructions that, when executed by the processing module, cause the processing module to perform functions that include: modifying an address received for a first memory access such that a more significant portion of the address is exchanged with a shifted portion which has a less significant position in the address, the shifted portion identifying a particular set in a first memory and the more significant portion identifying a block in the particular set, wherein modifying the address produces a first memory address; and performing the first memory access to the first memory using the first memory address.
Claim 20
Dependent Claim
74 words
The processor of claim 16 , wherein the operating instructions further comprise operating instructions that cause the processing module to perform the function of modifying the address by left-shifting the shifted portion of the address by N bits and inserting the more significant portion in the less significant position, wherein the less significant position lies between the shifted portion after shifting and a least significant portion, wherein the more significant portion includes N bits.
Claim 21
Dependent Claim
13 words
The processor of claim 17 , wherein the first memory is a cache.
Claim 22
Dependent Claim
15 words
The processor of claim 18 , wherein 2N stream buffers are maintained within the cache.
Claim 23
Dependent Claim
17 words
The processor of claim 19 , wherein the cache memory stores data relating to video graphics processing.
Claim 24
Dependent Claim
29 words
The processor of claim 20 , wherein the data relating to video graphics processing includes at least one of color data, primitive vertex coordinate data, and texture mapping data.
Claim 25
Dependent Claim
74 words
The processor of claim 16 , wherein the operating instructions further comprise operating instructions that cause the processing module to perform additional functions that include: determining that a second memory access to a second memory is required based on the first memory access; modifying one of the address and the first memory address to produce a second memory address; and performing the second memory access to the second memory using the second memory address.
Claim 26
Dependent Claim
61 words
The processor of claim 22 , wherein the processing module performs the additional function of modifying the first memory address to produce the second memory address by: discarding the more significant portion of the address; right-shifting the shifted portion of the address by N bits; and filling a most significant portion of the second memory address with a predetermined bit pattern.
References Cited (Backward Citations)
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Cited
US6128718A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-05 | 2005-05-07 | 2005-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-05 | 2009-05-07 | 2009-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-05 | 2013-05-07 | 2013-11-06 | $7700.00 | Window Closed / Lapsed |