Synchronizing circuit for generating internal signal synchronized to external signal

Claim 2

A synchronizing circuit comprising: an output circuit for outputting high level data and low level data, said output circuit having a first circuit for outputting said high level data in response to a first start signal having a period equal to a period of a clock signal and a second circuit for outputting said low level data in response to a second start signal having a period equal to the period of said clock signal; a first signal generation circuit supplied with said clock signal, said first signal generation circuit advancing a phase of said clock signal substantially by a total of a first delay time caused when said first circuit outputs high level data and a second delay time caused when said second circuit outputs low level data; a second signal generation circuit having a delay time substantially equal to said second delay time of said second circuit, said second signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said first start signal for starting said first circuit of said output circuit by using the delayed signal; and a third signal generation circuit having a delay time substantially equal to said first delay time of said first circuit, said third signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said second start signal for starting said second circuit of said output circuit by using the delayed signal.

Claim 3

The circuit according to claim 1 , wherein said first signal generation circuit comprises a delay locked loop.

Claim 4

The circuit according to claim 1 , wherein said first signal generation circuit comprises: an input buffer supplied with said clock signal; a delay line for delaying an output signal of said input buffer; a replica circuit for delaying an output signal of said delay line, said replica circuit having a delay time equal to a total delay time of said second and third signal generation circuits and said input buffer; and a phase comparator supplied with the output signal of said input buffer and an output signal of said replica circuit, said phase comparator detecting a phase difference between the output signal of said input buffer and the output signal of said replica circuit and controlling said delay line according to the detected phase difference.

Claim 5

The circuit according to claim 1 , wherein said first signal generation circuit comprises a mirror-type delay locked loop.

Claim 6

The circuit according to claim 4 , wherein said first signal generation circuit comprises: an input buffer supplied with said clock signal; a delay monitor supplied with an output signal of said input buffer, said delay monitor monitoring delay values of said input buffer and an output buffer; a first delay line supplied with an output signal of said delay monitor, said first delay line delaying the output signal of said delay monitor by one period of a clock signal outputted from said input buffer; and a second delay line for delaying a signal delayed by said first delay line by a time substantially equal to the delay time caused by said first delay line.

Claim 7

The circuit according to claim 3 , wherein said first signal generation circuit comprises a series circuit of said first circuit for outputting high level data, and the second circuit for outputting low level data.

Claim 8

A synchronizing circuit comprising: an input buffer supplied with a clock signal; a first delay circuit supplied with an output signal of said input buffer, said first delay circuit being varied in delay time; a first output buffer supplied with an output signal of said first delay circuit; a second output buffer supplied with the output signal of said first delay circuit; a first replica circuit supplied with an output signal of said first buffer, said first replica circuit having same configuration as that of a circuit portion of an output circuit for outputting a high level signal; a second replica circuit supplied with an output signal of said second buffer, said second replica circuit having same configuration as that of a circuit portion of an output circuit for outputting a low level signal; an output circuit supplied with output signals of said first and second replica circuits, said output circuit outputting data supplied from a memory cell in response to output signals of said first and second replica circuits; a second delay circuit supplied with the output signal of said first delay circuit, said second delay circuit having a third replica circuit comprising a replica circuit for said first and second output buffers and a fourth replica circuit said first and second replica circuits; a fifth replica circuit supplied with an output signal of said second delay circuit, said fifth replica circuit having same configuration as that of said input buffer; and a phase comparator for comparing a phase of an output signal of said fifth replica circuit with a phase of the output signal of said input buffer, said phase comparator controlling said first delay circuit in response to a phase difference between the output signal of said fifth replica circuit and the output signal of said input buffer.

Claim 9

A synchronizing circuit comprising: an input buffer supplied with a clock signal; a first delay circuit supplied with an output signal of said input buffer, said first delay circuit being varied in delay time; a first output buffer supplied with an output signal of said first delay circuit; a second output buffer supplied with the output signal of said first delay circuit; a first replica circuit supplied with an output signal of said first buffer, said first replica circuit having same configuration as that of a circuit portion of an output circuit for outputting a high level signal; a second replica circuit supplied with an output signal of said second buffer, said second replica circuit having same configuration as that of a circuit portion of an output circuit for outputting a low level signal; an output circuit supplied with output signals of said first and second replica circuits, said output circuit outputting data supplied from a memory cell in response to output signals of said first and second replica circuits; a second delay circuit supplied with the output signal of said first delay circuit, said second delay circuit having a third replica circuit comprising a replica circuit for said first and second output buffers and a fourth replica circuit said first and second replica circuits; a fifth replica circuit supplied with an output signal of said second delay circuit, said fifth replica circuit having same configuration as that of said input buffer; and a phase comparator for comparing a phase of an output signal of said fifth replica circuit with a phase of the output signal of said input buffer, said phase comparator controlling said first delay circuit in response to a phase difference between the output signal of said fifth replica circuit and the output signal of said input buffer.

Claim 10

The circuit according to claim 7 , wherein said output circuit comprises: a first logic circuit supplied with an input signal at a first input terminal thereof and supplied with an output signal of said first replica circuit at a second input terminal thereof; a second logic circuit supplied with an inverted signal of said input signal at a first input terminal thereof and supplied with an output signal of said second replica circuit at a second input terminal thereof; and a third logic circuit supplied with output signals of said first and second logic circuits at first and second input terminals thereof, respectively.

Claim 11

A synchronizing circuit comprising: a first output circuit supplied with first data outputted from a memory cell array, said first output circuit outputting the first data, said first output circuit having a first circuit for outputting high level data in response to a first start signal having a period equal to a period of a clock signal and a second circuit for outputting low level data in response to a second start signal having a period equal to the period of said clock signal; a second output circuit supplied with second data outputted from said memory cell array, said second output circuit outputting the second data, said second output circuit having a third circuit for outputting high level data in response to a third start signal having a period equal to a period of said clock signal and a fourth circuit for outputting low level data in response to a fourth start signal having a period equal to the period of said clock signal; a first synchronizing circuit for generating said first and second start signals in response to said clock signal; and a second synchronizing circuit for generating said third and fourth start signals in response to an inverted signal of said clock signal.

Claim 12

A synchronizing circuit comprising: a first output circuit supplied with first data outputted from a memory cell array, said first output circuit outputting the first data, said first output circuit having a first circuit for outputting high level data in response to a first start signal having a period equal to a period of a clock signal and a second circuit for outputting low level data in response to a second start signal having a period equal to the period of said clock signal; a second output circuit supplied with second data outputted from said memory cell array, said second output circuit outputting the second data, said second output circuit having a third circuit for outputting high level data in response to a third start signal having a period equal to a period of said clock signal and a fourth circuit for outputting low level data in response to a fourth start signal having a period equal to the period of said clock signal; a first synchronizing circuit for generating said first and second start signals in response to said clock signal; and a second synchronizing circuit for generating said third and fourth start signals in response to an inverted signal of said clock signal.

Claim 13

The circuit according to claim 9 , wherein said first synchronizing circuit comprises: a first signal generation circuit supplied with said clock signal, said first signal generation circuit advancing a phase of said clock signal substantially by a total of a first delay time caused when said first circuit outputs high level data and a second delay time caused when said second circuit outputs low level data; a second signal generation circuit having a delay time substantially equal to said second delay time of said second circuit, said second signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said first start signal for starting said first circuit of said first output circuit by using the delayed signal; and a third signal generation circuit having a delay time substantially equal to said first delay time of said first circuit, said third signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said second start signal for starting said second circuit of said first output circuit by using the delayed signal.

Claim 14

The circuit according to claim 9 , wherein said second synchronizing circuit comprises: a fourth signal generation circuit supplied with said clock signal, said fourth signal generation circuit advancing a phase of said clock signal substantially by a total of a third delay time caused when said third circuit outputs high level data and a fourth delay time caused when said fourth circuit outputs low level data; a fifth signal generation circuit having a delay time substantially equal to said fourth delay time of said fourth circuit, said fifth signal generation circuit delaying a signal outputted from said fourth signal generation circuit, and generating said third start signal for starting said third circuit of said second output circuit by using the delayed signal; and a sixth signal generation circuit having a delay time substantially equal to said third delay time of said third circuit, said sixth signal generation circuit delaying a signal outputted from said fourth signal generation circuit, and generating said fourth start signal for starting said fourth circuit of said second output circuit by using the delayed signal.

Claim 15

The circuit according to claim 10 , wherein said first output circuit comprises: a first tri-state buffer circuit supplied with first data read out from said memory cell array; and a first control signal generation circuit supplied with said first data, said first start signal, and said second start signal, said first control signal generation circuit generating a first control signal for controlling said first tri-state buffer circuit in response to said first data, said first start signal, and said second start signal.

Claim 16

The circuit according to claim 11 , wherein said second output circuit comprises: a second tri-state buffer circuit supplied with second data read out from said memory cell array; and a second control signal generation circuit supplied with said second data, said third start signal, and said fourth start signal, said second control signal generation circuit generating a second control signal for controlling said second tri-state buffer circuit in response to said second data, said third start signal, and said fourth start signal.

Claim 17

A synchronizing circuit comprising: a first buffer circuit supplied with first data outputted from a memory cell array, said first buffer circuit outputting the first data, said first buffer circuit having a first circuit for outputting high level data in response to a first start signal having a period equal to a period of a clock signal and a second circuit for outputting low level data in response to a second start signal having a period equal to the period of said clock signal; a second buffer circuit supplied with second data outputted from said memory cell array, said second buffer circuit outputting the second data, said second buffer circuit having a third circuit for outputting high level data in response to a third start signal having a period equal to a period of said clock signal and a fourth circuit for outputting low level data in response to a fourth start signal having a period equal to the period of said clock signal; an output circuit supplied with output signals of said first and second buffer circuits; a first synchronizing circuit for generating said first and second start signals in response to said clock signal; and a second synchronizing circuit for generating said third and fourth start signals in response to an inverted signal of said clock signal.

Claim 18

A synchronizing circuit comprising: a first buffer circuit supplied with first data outputted from a memory cell array, said first buffer circuit outputting the first data, said first buffer circuit having a first circuit for outputting high level data in response to a first start signal having a period equal to a period of a clock signal and a second circuit for outputting low level data in response to a second start signal having a period equal to the period of said clock signal; a second buffer circuit supplied with second data outputted from said memory cell array, said second buffer circuit outputting the second data, said second buffer circuit having a third circuit for outputting high level data in response to a third start signal having a period equal to a period of said clock signal and a fourth circuit for outputting low level data in response to a fourth start signal having a period equal to the period of said clock signal; an output circuit supplied with output signals of said first and second buffer circuits; a first synchronizing circuit for generating said first and second start signals in response to said clock signal; and a second synchronizing circuit for generating said third and fourth start signals in response to an inverted signal of said clock signal.

Claim 19

The circuit according to claim 14 , wherein said first buffer circuit comprises: a first tri-state buffer circuit supplied with first data read out from said memory cell array; and a first control signal generation circuit supplied with said first data, said first start signal, and said second start signal, said first control signal generation circuit generating a first control signal for controlling said first tri-state buffer circuit in response to said first data, said first start signal, and said second start signal.

Claim 20

The circuit according to claim 14 , wherein said second buffer circuit comprises: a second tri-state buffer circuit supplied with second data read out from said memory cell array; and a second control signal generation circuit supplied with said second data, said third start signal, and said fourth start signal, said second control signal generation circuit generating a second control signal for controlling said second tri-state buffer circuit in response to said second data, said third start signal, and said fourth start signal.

Claim 21

The circuit according to claim 16 , wherein said output circuit comprises a third tri-state buffer circuit, and a size of each of transistors included in said first and second tri-state buffer circuits is set so as to be smaller than a size of a transistor included in said third tri-state buffer circuit.

Claim 22

A synchronizing circuit comprising: a parallel-to-serial conversion circuit supplied with first and second data outputted from a memory cell array, said parallel-to-serial conversion circuit successively outputting said first and second data; a shift register supplied with an output signal of said parallel-to-serial conversion circuit, said shift register having a first circuit for outputting high level data and a second circuit for outputting low level data; an output circuit supplied with an output signal of said shift register; a control circuit connected to said shift register, said control circuit generating a control signal in response to the output signal of said parallel-to-serial conversion circuit, a first start signal for outputting high level data, and a second start signal for outputting low level data, each of said first and second start signals having a period equal to a period of said clock signal, said control signal being supplied to said shift register; and a start signal generation circuit for generating said first and second start signals in response to said clock signal.

Claim 23

A synchronizing circuit comprising: a parallel-to-serial conversion circuit supplied with first and second data outputted from a memory cell array, said parallel-to-serial conversion circuit successively outputting said first and second data; a shift register supplied with an output signal of said parallel-to-serial conversion circuit, said shift register having a first circuit for outputting high level data and a second circuit for outputting low level data; an output circuit supplied with an output signal of said shift register; a control circuit connected to said shift register, said control circuit generating a control signal in response to the output signal of said parallel-to-serial conversion circuit, a first start signal for outputting high level data, and a second start signal for outputting low level data, each of said first and second start signals having a period equal to a period of said clock signal, said control signal being supplied to said shift register; and a start signal generation circuit for generating said first and second start signals in response to said clock signal.

Claim 24

The circuit according to claim 18 , wherein said start signal generation circuit comprises: a first signal generation circuit supplied with said clock signal, said first signal generation circuit advancing a phase of said clock signal substantially by a total of a first delay time caused when said first circuit outputs high level data and a second delay time caused when said second circuit outputs low level data; a second signal generation circuit having a delay time substantially equal to said second delay time of said second circuit, said second signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said first start signal for starting said first circuit of said shift register by using the delayed signal; and a third signal generation circuit having a delay time substantially equal to said first delay time of said first circuit, said third signal generation circuit delaying a signal outputted from said first signal generation circuit, and generating said second start signal for starting said second circuit of said shift register by using the delayed signal.

Claim 25

The circuit according to claim 18 , wherein said parallel-to-serial conversion circuit comprises: a first buffer circuit supplied with said first data, said first buffer circuit outputting first data in response to a first control signal; and a second buffer circuit supplied with said second data, said second buffer circuit outputting second data in response to a second control signal.