US6311317B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pre-synthesis test point insertion
Assignee: Synopsys Inc
•
Filing: 1999-03-31
•
Granted: 2001-10-30
•
Expires: 2019-03-31
Abstract
Abstract A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality. The actual test point circuit may also be merged with other circuitries of the integrated circuit to produce a more efficient design.
Inventors
- 👤 Ajay Khoche
- 👤 Harbinder Singh
- 👤 Dhiraj Goswami
- 👤 Denis Martin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
156 words
In a computer controlled electronic design automation system, a computer implemented method of inserting test points in an integrated circuit design, said method comprising the steps of: a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets; b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point; c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist; and d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.
Claim 2
Dependent Claim
156 words
In a computer controlled electronic design automation system, a computer implemented method of inserting test points in an integrated circuit design, said method comprising the steps of: a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets; b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point; c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist; and d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.
Claim 3
Dependent Claim
28 words
The method as recited in claim 1 wherein said logic synthesis process removes logic redundancy in said generic test point circuit to generate said actual test point circuit.
Claim 4
Dependent Claim
46 words
The method as recited in claim 1 wherein said generic test point circuit comprises: a first input port for receiving a test mode signal; a second input port for receiving a test point enable signal; and a third input port for receiving a test data signal.
Claim 5
Dependent Claim
44 words
The method as recited in claim 3 further comprising the step of configuring said generic test point circuit for said specific function by setting said test mode signal, said test point enable signal, and said test data signal to a set of predetermined values.
Claim 6
Dependent Claim
58 words
The method as recited in claim 4 further comprising the steps of: splitting said particular net into a source segment and a target segment; coupling a fourth input port of said generic test point circuit to said source segment to receive input data; and coupling an output port of said generic test point circuit to said target segment.
Claim 7
Dependent Claim
27 words
The method as recited in claim 4 further comprising the step of coupling a tri-stated output port of said generic test point circuit to said particular net.
Claim 8
Dependent Claim
32 words
The method as recited in claim 4 wherein implementation of said actual test point circuit is dictated by said test mode signal, said test point enable signal and said test data signal.
Claim 9
Dependent Claim
163 words
A computer readable memory having computer-readable program code embodied therein for causing a computer system to perform a method of inserting test points within an integrated circuit design, said method comprising the steps of: a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets; b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point; c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist; and d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.
Claim 10
Dependent Claim
163 words
A computer readable memory having computer-readable program code embodied therein for causing a computer system to perform a method of inserting test points within an integrated circuit design, said method comprising the steps of: a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets; b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point; c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist; and d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.
Claim 11
Dependent Claim
30 words
The computer readable memory as recited in claim 8 wherein said logic synthesis process removes logic redundancy in said generic test point circuit to generate said actual test point circuit.
Claim 12
Dependent Claim
48 words
The computer readable memory as recited in claim 8 wherein said generic test point circuit comprises: a first input port for receiving a test mode signal; a second input port for receiving a test point enable signal; and a third input port for receiving a test data signal.
Claim 13
Dependent Claim
49 words
The computer readable memory as recited in claim 10 wherein said method further comprises the step of configuring said generic test point circuit for said specific function by setting said test mode signal, said test point enable signal, and said test data signal to a set of predetermined values.
Claim 14
Dependent Claim
63 words
The computer readable memory as recited in claim 11 wherein said method further comprises the steps of: splitting said particular net into a source segment and a target segment; coupling a fourth input port of said generic test point circuit to said source segment to receive input data; and coupling an output port of said generic test point circuit to said target segment.
Claim 15
Dependent Claim
32 words
The computer readable memory as recited in claim 11 wherein said method further comprises the step of coupling a tri-stated output port of said generic test point circuit to said particular net.
Claim 16
Dependent Claim
34 words
The computer readable memory as recited in claim 11 wherein implementation of said actual test point circuit is dictated by said test mode signal, said test point enable signal and said test data signal.
Claim 17
Dependent Claim
181 words
An electronic design automation system comprising: a processor; a bus coupled to said processor; and a computer readable memory coupled to said bus and having stored therein computer readable program code for causing said electronic design automation system to perform a method of test point insertion, said method comprising the steps of: a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets; b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point; c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist; and d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.
Claim 18
Dependent Claim
181 words
An electronic design automation system comprising: a processor; a bus coupled to said processor; and a computer readable memory coupled to said bus and having stored therein computer readable program code for causing said electronic design automation system to perform a method of test point insertion, said method comprising the steps of: a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets; b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point; c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist; and d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.
Claim 19
Dependent Claim
30 words
The computer readable memory as recited in claim 15 wherein said logic synthesis process removes logic redundancy in said generic test point circuit to generate said actual test point circuit.
Claim 20
Dependent Claim
48 words
The computer readable memory as recited in claim 15 wherein said generic test point circuit comprises: a first input port for receiving a test mode signal; a second input port for receiving a test point enable signal; and a third input port for receiving a test data signal.
Claim 21
Dependent Claim
49 words
The computer readable memory as recited in claim 17 wherein said method further comprises the step of configuring said generic test point circuit for said specific function by setting said test mode signal, said test point enable signal, and said test data signal to a set of predetermined values.
Claim 22
Dependent Claim
63 words
The computer readable memory as recited in claim 18 wherein said method further comprises the steps of: splitting said particular net into a source segment and a target segment; coupling a fourth input port of said generic test point circuit to said source segment to receive input data; and coupling an output port of said generic test point circuit to said target segment.
Claim 23
Dependent Claim
32 words
The computer readable memory as recited in claim 18 wherein said method further comprises the step of coupling a tri-stated output port of said generic test point circuit to said particular net.
Claim 24
Dependent Claim
34 words
The computer readable memory as recited in claim 18 wherein implementation of said actual test point circuit is dictated by said test mode signal, said test point enable signal and said test data signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-29 | 2005-04-30 | 2005-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-29 | 2009-04-30 | 2009-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-29 | 2013-04-30 | 2013-10-30 | $7700.00 | Window Closed / Lapsed |