US6297987B1
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Magnetoresistive spin-injection diode
Assignee: UNTIED STATES OF AMERICA NAVY THE, Secretary of
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Filing: 1999-09-30
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Granted: 2001-10-02
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Expires: 2019-09-30
Abstract
Abstract A spin injected diode suitable for nonvolatile memory applications is made of a semiconducting channel capable of carrying current, a single ferromagnetic layer, and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting layer and to inhibit interdiffusion of the ferromagnetic material and the semiconductor. During diode readout the output modulation of the diode can be sensed either as the interface resistance between the semiconducting channel and the ferromagnetic layer, or as the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface. Two of these spin injected diodes can be combined to form a spin injected field effect transistor. This transistor has a first ferromagnetic layer having a first coercivity and a second ferromagnetic layer having a second coercivity smaller than the first coercivity which are spaced apart. A gate is situated between the ferromagnetic layers and includes an insulating layer situated below the gate and between the two ferromagnetic layers. A semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times. A key component is a barrier layer between the semiconducting channel and the two ferromagnetic layers which performs the same functions as in the diode.
Inventors
- 👤 Mark B. Johnson
- 👤 Brian Bennett
- 👤 Philip R Hammar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:32
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/385; G; G11; G11C; G11C11/00; G11C11/02; G11C11/14; G11C11/15
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
115 words
A spin injected diode suitable for nonvolatile memory applications comprising a semiconducting channel capable of carrying current, a single ferromagnetic layer, and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the ferromagnetic material and the semiconducting channel, wherein said ferromagnetic layer includes an electrical connector for connecting to a readout device, and wherein during diode readout an output modulation being sensed is either (a) an interface resistance between the semiconducting channel and the ferromagnetic layer, or (b) an output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface.
Claim 2
Dependent Claim
115 words
A spin injected diode suitable for nonvolatile memory applications comprising a semiconducting channel capable of carrying current, a single ferromagnetic layer, and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the ferromagnetic material and the semiconducting channel, wherein said ferromagnetic layer includes an electrical connector for connecting to a readout device, and wherein during diode readout an output modulation being sensed is either (a) an interface resistance between the semiconducting channel and the ferromagnetic layer, or (b) an output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface.
Claim 3
Dependent Claim
23 words
A spin injected diode according to claim 1 , wherein the current carried by the semiconducting channel can be either electrons or holes.
Claim 4
Dependent Claim
33 words
A spin injected diode according to claim 1 , wherein the semiconducting channel has an intrinsic electric field that splits spin states in the semiconducting channel and results in a spin-dependent interface resistance.
Claim 5
Dependent Claim
27 words
A spin injected diode according to claim 3 , wherein the semiconducting channel has an intrinsic electric field due to the polar nature of the channel material.
Claim 6
Dependent Claim
36 words
A spin injected diode according to claim 1 , wherein a confining potential of carriers in the semiconducting channel has asymmetry such that there is a large electric field perpendicular to the plane of the carriers.
Claim 7
Dependent Claim
20 words
A spin injected diode according to claim 5 , wherein the asymmetry in the semiconducting channel is structural or gate-induced.
Claim 8
Dependent Claim
17 words
A spin injected diode according to claim 1 , wherein the semiconducting channel is a 2DEG layer.
Claim 9
Dependent Claim
21 words
A spin injected diode according to claim 1 , wherein the thickness of the barrier layer is at least 10 nm.
Claim 10
Dependent Claim
17 words
A spin injected diode according to claim 1 , wherein the semiconducting channel is a III-V compound.
Claim 11
Dependent Claim
26 words
A spin injected diode according to claim 1 , wherein the modulation being sensed is the interface resistance between the semiconducting channel and the ferromagnetic layer.
Claim 12
Dependent Claim
28 words
A spin injected diode according to claim 1 , wherein the magnetization of the single ferromagnetic layer during readout is oriented in either one of two opposite directions.
Claim 13
Dependent Claim
38 words
A spin injected diode according to claim 1 , wherein the output modulation being sensed is the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface.
Claim 14
Dependent Claim
23 words
A spin injected diode according to claim 1 , wherein the impedance of the diode is from about 100 Ω to 10 KΩ.
Claim 15
Dependent Claim
19 words
A spin injected diode according to claim 1 , wherein the single ferromagnetic layer is a single ferromagnetic film.
Claim 16
Dependent Claim
185 words
A memory cell having a spin injected diode suitable for nonvolatile memory applications for storing a data state corresponding to one of a first and a second logical data value, said memory cell comprising: a semiconducting channel capable of carrying current, a single ferromagnetic layer, and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the ferromagnetic layer and the semiconducting channel, wherein said memory cell stores the first logical value when the ferromagnetic layer has a magnetic field applied in one direction, and where said memory element stores the second logical value when the magnetic field is applied to the ferromagnetic layer in the opposite direction, and wherein said ferromagnetic layer includes an electrical connector for connecting to a readout device, and wherein during diode readout an output modulation being sensed is either (a) an interface resistance between the semiconducting channel and the ferromagnetic layer, or (b) the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface.
Claim 17
Dependent Claim
185 words
A memory cell having a spin injected diode suitable for nonvolatile memory applications for storing a data state corresponding to one of a first and a second logical data value, said memory cell comprising: a semiconducting channel capable of carrying current, a single ferromagnetic layer, and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the ferromagnetic layer and the semiconducting channel, wherein said memory cell stores the first logical value when the ferromagnetic layer has a magnetic field applied in one direction, and where said memory element stores the second logical value when the magnetic field is applied to the ferromagnetic layer in the opposite direction, and wherein said ferromagnetic layer includes an electrical connector for connecting to a readout device, and wherein during diode readout an output modulation being sensed is either (a) an interface resistance between the semiconducting channel and the ferromagnetic layer, or (b) the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface.
Claim 18
Independent Claim
147 words
A method of operating a hybrid magnetic spin injected diode device comprising: a semiconducting channel capable of carrying current, a single ferromagnetic layer, said ferromagnetic layer including an electrical connector for connecting to a readout device; and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the ferromagnetic layer and the semiconducting channel, said method comprising: applying a magnetic field on the single ferromagnetic layer in either one direction or in the opposite direction to store a first logical value or a second logical value; and reading the diode output modulation being sensed by either determining (a) an interface resistance between the semiconducting channel and the ferromagnetic layer, or (b) the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface.
Claim 19
Independent Claim
147 words
A method of operating a hybrid magnetic spin injected diode device comprising: a semiconducting channel capable of carrying current, a single ferromagnetic layer, said ferromagnetic layer including an electrical connector for connecting to a readout device; and a barrier layer between the semiconducting channel and the ferromagnetic layer to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the ferromagnetic layer and the semiconducting channel, said method comprising: applying a magnetic field on the single ferromagnetic layer in either one direction or in the opposite direction to store a first logical value or a second logical value; and reading the diode output modulation being sensed by either determining (a) an interface resistance between the semiconducting channel and the ferromagnetic layer, or (b) the output voltage between the semiconducting channel and the ferromagnetic layer when flowing current through the channel and not through the interface.
Claim 20
Dependent Claim
153 words
A magnetic spin injected field effect transistor device comprising: a first ferromagnetic layer having a first coercivity; a second ferromagnetic layer having a second coercivity smaller than said first coercivity, and spaced apart from said first ferromagnetic layer; a gate situated between the first and second ferromagnetic layers and including an insulating layer situated below the gate and between the two ferromagnetic layers; a semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate that forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times; and a barrier layer between the semiconducting channel and the first and second ferromagnetic layers to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the first and second ferromagnetic layers and the semiconducting channel.
Claim 21
Dependent Claim
153 words
A magnetic spin injected field effect transistor device comprising: a first ferromagnetic layer having a first coercivity; a second ferromagnetic layer having a second coercivity smaller than said first coercivity, and spaced apart from said first ferromagnetic layer; a gate situated between the first and second ferromagnetic layers and including an insulating layer situated below the gate and between the two ferromagnetic layers; a semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate that forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times; and a barrier layer between the semiconducting channel and the first and second ferromagnetic layers to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the first and second ferromagnetic layers and the semiconducting channel.
Claim 22
Dependent Claim
53 words
The device of claim 17 , wherein the first ferromagnetic layer can be set to a first magnetization orientation, the second ferromagnetic layer can be set to a second magnetization orientation, and an impedance to spin polarized charge carrier current flow in said device is based on the first and second magnetization orientations.
Claim 23
Dependent Claim
39 words
The device of claim 18 , wherein the impedance to spin polarized electron current flow is relatively low when the first and second magnetization orientations are parallel, and relatively high when the first and second magnetization orientations are anti-parallel.
Claim 24
Dependent Claim
17 words
The device of claim 17 , wherein both the first and second ferromagnetic layers are magnetically anisotropic.
Claim 25
Dependent Claim
225 words
A memory cell having a magnetic spin injected transistor for nonvolatile memory applications for storing a data state corresponding to one of a first and a second logical data value, said memory cell comprising: a first ferromagnetic layer having a first coercivity and having a first magnetization orientation; a second ferromagnetic layer, spaced apart from said first ferromagnetic layer, having a second coercivity smaller than said first coercivity and having a second alterable magnetization orientation; a gate situated between the first and second ferromagnetic layers; a semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate that forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times; and a barrier layer between the semiconducting channel and the first and second ferromagnetic layers to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the first and second ferromagnetic layers and the semiconducting channel; said gate controlling the electrical conductance of the semiconducting channel layer in response to a cell select signal; wherein said memory cell stores the first logical value when the first and second magnetization orientations are aligned, and the second logical value when the first and second magnetization orientations are opposite.
Claim 26
Dependent Claim
225 words
A memory cell having a magnetic spin injected transistor for nonvolatile memory applications for storing a data state corresponding to one of a first and a second logical data value, said memory cell comprising: a first ferromagnetic layer having a first coercivity and having a first magnetization orientation; a second ferromagnetic layer, spaced apart from said first ferromagnetic layer, having a second coercivity smaller than said first coercivity and having a second alterable magnetization orientation; a gate situated between the first and second ferromagnetic layers; a semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate that forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times; and a barrier layer between the semiconducting channel and the first and second ferromagnetic layers to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the first and second ferromagnetic layers and the semiconducting channel; said gate controlling the electrical conductance of the semiconducting channel layer in response to a cell select signal; wherein said memory cell stores the first logical value when the first and second magnetization orientations are aligned, and the second logical value when the first and second magnetization orientations are opposite.
Claim 27
Dependent Claim
51 words
The device of claim 21 , wherein the data state stored in the cell can be read by applying the control signal and measuring a spin polarized current which flows between the ferromagnetic layers in said device, the current in said device being based on the first and second magnetization orientations.
Claim 28
Dependent Claim
80 words
The device of claim 22 , further including a wire for inductively coupling said second ferromagnetic layer with a magnetic field generated by an input data signal on said wire, the input data signal having one of a first and a second current value corresponding to said first and second logical data values respectively, and whereby the second layer magnetization orientation can be altered by the magnetic field to become one of aligned and opposite to the first layer magnetization.
Claim 29
Dependent Claim
20 words
The cell of claim 23 , wherein the memory is retained until a different state is written to said cell.
Claim 30
Dependent Claim
25 words
The cell of claim 21 , wherein the semiconducting channel isolates the memory cell when said cell is not selected by said cell select signal.
Claim 31
Independent Claim
298 words
A method of operating a hybrid magnetic spin injected-field effect transistor device comprising a first ferromagnetic layer having a first coercivity and having a first magnetization orientation; a second ferromagnetic layer, spaced apart from said first ferromagnetic layer, having a second coercivity smaller than said first coercivity and having a second alterable magnetization orientation; a gate situated between the first and second ferromagnetic layers; a semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate that forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times; and a barrier layer between the semiconducting channel and the first and second ferromagnetic layers to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the first and second ferromagnetic layers and the semiconducting channel; said gate controlling the electrical conductance of the semiconducting channel layer in response to a cell select signal; said method comprising: providing a current of spin polarized charge carriers to flow from said first ferromagnetic layer to said second ferromagnetic layer; controlling the flow of spin polarized charge carriers between the two layers by applying said control signal to said gate of the field effect transistor having a channel interposed between the two layers; and controlling the quantity of spin polarized current flowing in the device by aligning a second magnetization orientation state of the second ferromagnetic layer relative to a first magnetization orientation state of the first ferromagnetic layer; whereby when said control signal is applied to said gate, the amount of spin polarized current which flows between the ferromagnetic layers in said device is based on the first and second magnetization orientations.
Claim 32
Independent Claim
298 words
A method of operating a hybrid magnetic spin injected-field effect transistor device comprising a first ferromagnetic layer having a first coercivity and having a first magnetization orientation; a second ferromagnetic layer, spaced apart from said first ferromagnetic layer, having a second coercivity smaller than said first coercivity and having a second alterable magnetization orientation; a gate situated between the first and second ferromagnetic layers; a semiconducting channel layer beneath the first and second ferromagnetic layers and beneath the gate that forms a low impedance electrical path between the first and second ferromagnetic layers when a control signal is applied to the gate and a high impedance electrical path between these ferromagnetic layers at all other times; and a barrier layer between the semiconducting channel and the first and second ferromagnetic layers to protect the integrity of the semiconducting channel and to inhibit interdiffusion of the first and second ferromagnetic layers and the semiconducting channel; said gate controlling the electrical conductance of the semiconducting channel layer in response to a cell select signal; said method comprising: providing a current of spin polarized charge carriers to flow from said first ferromagnetic layer to said second ferromagnetic layer; controlling the flow of spin polarized charge carriers between the two layers by applying said control signal to said gate of the field effect transistor having a channel interposed between the two layers; and controlling the quantity of spin polarized current flowing in the device by aligning a second magnetization orientation state of the second ferromagnetic layer relative to a first magnetization orientation state of the first ferromagnetic layer; whereby when said control signal is applied to said gate, the amount of spin polarized current which flows between the ferromagnetic layers in said device is based on the first and second magnetization orientations.
Claim 33
Dependent Claim
49 words
The method of claim 26 , wherein aligning of the second magnetization orientation state of the second ferromagnetic layer relative to the first magnetization orientation state of the first ferromagnetic layer can be changed by inductively coupling the second ferromagnetic layer with a write line generating a magnetic field.
Claim 34
Dependent Claim
44 words
The method of claim 27 , wherein the magnetic field from the write line can set the second magnetization orientation to either of two stable non-volatile states, and these states represent a binary value of a data bit to be stored in the device.
Claim 35
Dependent Claim
51 words
The method of claim 28 , further including a step of reading the data bit stored in the device by applying said control signal to said gate, and comparing an output signal generated by the spin polarized current with a reference value to determine the data bit stored in said device.
Claim 36
Dependent Claim
71 words
The method of claim 27 , wherein the magnetic field from the write line can set the second magnetization orientation to either of two stable non-volatile states, and these states represent a boolean function binary data value relating one or more input logic signals, and wherein the second magnetization orientation stores the boolean function binary data value and only changes in response to certain predetermined combinations of the input logic signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-01 | 2005-04-02 | 2005-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-01 | 2009-04-02 | 2009-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-01 | 2013-04-02 | 2013-10-02 | $7700.00 | Window Closed / Lapsed |