Configuring vectors of logical storage units for data storage partitioning and sharing

Claim 5

The method as claimed in claim 2 , wherein the modulus of the stride (S) is computed from the address specified by the host processor by computing a difference between the address specified by the host processor and the beginning address of the vector of logical storage units that have been configured for the host processor, and computing the modulus of the difference and the stride (S), and wherein the method includes finding that the address specified by the host processor is an address within the vector of addresses of logical storage units that have been configured for access by the host processor when the modulus is zero, and finding that the address specified by the host processor is not an address within the vector of addresses of logical storage units that have been configured for access by the host processor when the modulus is not zero.

Claim 8

A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and wherein the storage controller is programmed to store the vector specification in memory of the data storage subsystem, wherein the vetor specification stored in memory of the data storage subsystem includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of a number (N) of addressable logical storage units in the series of addressable logical storage units.

Claim 9

A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; and wherein the storage controller is programmed to store the vector specification in memory of the data storage subsystem, wherein the vetor specification stored in memory of the data storage subsystem includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of a number (N) of addressable logical storage units in the series of addressable logical storage units.

Claim 10

A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the storage controller is programmed to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor; and wherein the storage controller is programmed to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor by computing a modulus of the stride (S) from the address specified by the host processor.

Claim 11

A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the storage controller is programmed to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor; and wherein the storage controller is programmed to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor by computing a modulus of the stride (S) from the address specified by the host processor.

Claim 12

The data storage subsystem as claimed in claim 6 , wherein the storage controller is programmed to compute the modulus of the stride (S) from the address specified by the host processor by computing a difference between the address specified by the host processor and the beginning address of the vector of logical storage units that have been configured for the host processor, and computing the modulus of the difference and the stride (S), and wherein the storage controller is programmed to find that the address specified by the host processor is an address within the vector of addresses of logical storage units that have been configured for access by the host processor when the modulus is zero.

Claim 13

A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the storage controller is programmed to assign a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and to store in memory of the data storage subsystem a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units; wherein the storage controller is programmed to respond to a request from the host processor for access to a specified logical unit number by checking whether or not the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, and when the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, computing an address of a logical storage unit from the specified logical unit number, and accessing the logical storage unit having the address computed from the specified logical unit number; and wherein the range of contiguous logical unit numbers used by the host processor begins with a beginning logical unit number, and wherein the storage controller is programmed to compute a difference between the specified logical unit number and the beginning logical unit number, multiply the difference by the stride (S) to produce a product, and add the product to the beginning address (BEGIN) of the vector in order to compute the address of the logical storage unit computed from the specified logical unit number.

Claim 14

A data storage subsystem comprising, in combination: data storage; and a storage controller coupled to the data storage for controlling access to the data storage, the storage controller having at least one data port for linking the data storage to a plurality of host processors for transfer of data between the data storage and the host processors, wherein the storage controller is programmed to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the storage controller is programmed to assign a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and to store in memory of the data storage subsystem a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units; wherein the storage controller is programmed to respond to a request from the host processor for access to a specified logical unit number by checking whether or not the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, and when the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, computing an address of a logical storage unit from the specified logical unit number, and accessing the logical storage unit having the address computed from the specified logical unit number; and wherein the range of contiguous logical unit numbers used by the host processor begins with a beginning logical unit number, and wherein the storage controller is programmed to compute a difference between the specified logical unit number and the beginning logical unit number, multiply the difference by the stride (S) to produce a product, and add the product to the beginning address (BEGIN) of the vector in order to compute the address of the logical storage unit computed from the specified logical unit number.

Claim 15

A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the program is executable by the storage controller to store the vector specification in memory of the storage controller, wherein the vector specification stored in memory of the storage controller includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of a number (N) of addressable logical storage units in the series of addressable logical storage units.

Claim 16

A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the program is executable by the storage controller to store the vector specification in memory of the storage controller, wherein the vector specification stored in memory of the storage controller includes a specification of the beginning address (BEGIN), a specification of the stride (S), and a specification of a number (N) of addressable logical storage units in the series of addressable logical storage units.

Claim 17

A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the program is executable by the storage controller to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor; and wherein the program is executable by the storage controller to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor by computing a modulus of the stride (S) from the address specified by the host processor, and finding that the address specified by the host processor is an address within the vector of addresses of logical storage units that have been configured for access by the host processor when the modulus is zero.

Claim 18

A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the program is executable by the storage controller to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor, in order to grant the host processor access to a logical storage unit having the specified address when the specified address is within the vector of addresses of logical storage units that have been configured for access by the host processor, and to deny the host processor access to a logical storage unit having the specified address when the specified address is not within the vector of logical storage units that have been configured for access by the host processor; and wherein the program is executable by the storage controller to determine whether or not an address specified by a host processor is an address within a vector of addresses of logical storage units that have been configured for access by the host processor by computing a modulus of the stride (S) from the address specified by the host processor, and finding that the address specified by the host processor is an address within the vector of addresses of logical storage units that have been configured for access by the host processor when the modulus is zero.

Claim 19

The machine-readable program storage device as claimed in claim 10 , wherein the program is executable by the storage controller to compute the modulus of the stride (S) from the address specified by the host processor by computing a difference between the address specified by the host processor and the beginning address of the vector of logical storage units that have been configured for the host processor, and computing the modulus of the difference and the stride (S), and wherein the program is executable by the storage controller to find that the address specified by the host processor is an address within the vector of addresses of logical storage units that have been configured for access by the host processor when the modulus is zero, and to find that the address specified by the host processor is not an address within the vector of addresses of logical storage units that have been configured for access by the host processor when the modulus is not zero.

Claim 20

A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the program is executable by the storage controller to assign a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and to store in memory of the storage controller a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units; wherein the program is executable by the storage controller to respond to a request from the host processor for access to a specified logical unit number by checking whether or not the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, and when the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, computing an address of a logical storage unit from the specified logical unit number, and accessing the logical storage unit having the address computed from the specified logical unit number; and wherein the range of contiguous logical unit numbers used by the host processor begins with a beginning logical unit number, and wherein the program is executable by the storage controller to compute a difference between the specified logical unit number and the beginning logical unit number, multiply the difference by the stride (S) to produce a product, and add the product to the beginning address (BEGIN) of the vector in order to compute the address of the logical storage unit computed from the specified logical unit number.

Claim 21

A machine-readable program storage device containing a program for a storage controller for controlling access of a plurality of host processors to data storage, wherein the program is executable by the storage controller to access addressable logical storage units of the data storage, and to restrict access of the host processors to the data storage by assigning to each host processor a respective subset of the data storage to which access of said each host processor is restricted, wherein the assignment of at least one respective subset includes at least one vector specification of a series of the addressable logical storage units, the addressable logical storage units in the series of addressable logical storage units having addresses that form a vector, the vector including a beginning address (BEGIN) and a stride (S) that is a difference between neighboring addresses of the addressable logical storage units in the series of addressable logical storage units, such that the addresses of the logical storage units in the series are BEGIN, BEGIN+S, BEGIN+2S, . . . , and wherein the stride (S) is a non-zero integer different from one; wherein the program is executable by the storage controller to assign a range of contiguous logical unit numbers used by a host processor to the vector specification of a series of the addressable logical storage units to establish a mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units, and to store in memory of the storage controller a specification of the mapping between the range of contiguous logical unit numbers used by the host processor and the series of the addressable logical storage units; wherein the program is executable by the storage controller to respond to a request from the host processor for access to a specified logical unit number by checking whether or not the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, and when the specified logical unit number is within the range of contiguous logical unit numbers used by the host processor, computing an address of a logical storage unit from the specified logical unit number, and accessing the logical storage unit having the address computed from the specified logical unit number; and wherein the range of contiguous logical unit numbers used by the host processor begins with a beginning logical unit number, and wherein the program is executable by the storage controller to compute a difference between the specified logical unit number and the beginning logical unit number, multiply the difference by the stride (S) to produce a product, and add the product to the beginning address (BEGIN) of the vector in order to compute the address of the logical storage unit computed from the specified logical unit number.